#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
92bb2cd4 |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
clk: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
2242ac5d |
|
25-Jul-2022 |
Jesse Taube <mr.bossman075@gmail.com> |
clk: imx: Add i.MXRT11xx pllv3 variant The i.MXRT11 series has two new pll types but are variants of existing. This patch adds the ability to read one of the pll types' frequency as it can't be changed unlike the generic pll it also has the division factors swapped. Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com> |
#
0cf207ec |
|
27-Sep-2021 |
Wolfgang Denk <wd@denx.de> |
WS cleanup: remove SPACE(s) followed by TAB Signed-off-by: Wolfgang Denk <wd@denx.de> |
#
9042bf6f |
|
24-Mar-2021 |
Simon Glass <sjg@chromium.org> |
clk: Update drivers to use -EINVAL At present some drivers use -ENOSUPP to indicate that an unknown or unsupported clock is used. Most use -EINVAL, indicating an invalid value, so convert everything to that. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> |
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de> |
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de> |
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de> |
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> |
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> |
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> |
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> |
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de> |
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de> |
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de> |
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> |
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de> |
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de> |
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de> |
#
92bb2cd4 |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
clk: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
2242ac5d |
|
25-Jul-2022 |
Jesse Taube <mr.bossman075@gmail.com> |
clk: imx: Add i.MXRT11xx pllv3 variant The i.MXRT11 series has two new pll types but are variants of existing. This patch adds the ability to read one of the pll types' frequency as it can't be changed unlike the generic pll it also has the division factors swapped. Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com> |
#
0cf207ec |
|
27-Sep-2021 |
Wolfgang Denk <wd@denx.de> |
WS cleanup: remove SPACE(s) followed by TAB Signed-off-by: Wolfgang Denk <wd@denx.de> |
#
9042bf6f |
|
24-Mar-2021 |
Simon Glass <sjg@chromium.org> |
clk: Update drivers to use -EINVAL At present some drivers use -ENOSUPP to indicate that an unknown or unsupported clock is used. Most use -EINVAL, indicating an invalid value, so convert everything to that. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> |
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de> |
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de> |
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de> |
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> |
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> |
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> |
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> |
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de> |
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de> |
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de> |
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> |
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de> |
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de> |
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de> |
#
2242ac5d |
|
25-Jul-2022 |
Jesse Taube <mr.bossman075@gmail.com> |
clk: imx: Add i.MXRT11xx pllv3 variant The i.MXRT11 series has two new pll types but are variants of existing. This patch adds the ability to read one of the pll types' frequency as it can't be changed unlike the generic pll it also has the division factors swapped. Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com> |
#
0cf207ec |
|
27-Sep-2021 |
Wolfgang Denk <wd@denx.de> |
WS cleanup: remove SPACE(s) followed by TAB Signed-off-by: Wolfgang Denk <wd@denx.de> |
#
9042bf6f |
|
24-Mar-2021 |
Simon Glass <sjg@chromium.org> |
clk: Update drivers to use -EINVAL At present some drivers use -ENOSUPP to indicate that an unknown or unsupported clock is used. Most use -EINVAL, indicating an invalid value, so convert everything to that. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> |
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de> |
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de> |
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de> |
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> |
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> |
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> |
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> |
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de> |
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de> |
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de> |
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> |
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de> |
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de> |
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de> |
#
0cf207ec |
|
27-Sep-2021 |
Wolfgang Denk <wd@denx.de> |
WS cleanup: remove SPACE(s) followed by TAB Signed-off-by: Wolfgang Denk <wd@denx.de> |
#
9042bf6f |
|
24-Mar-2021 |
Simon Glass <sjg@chromium.org> |
clk: Update drivers to use -EINVAL At present some drivers use -ENOSUPP to indicate that an unknown or unsupported clock is used. Most use -EINVAL, indicating an invalid value, so convert everything to that. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> |
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de> |
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de> |
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de> |
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> |
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> |
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> |
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> |
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de> |
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de> |
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de> |
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> |
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de> |
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de> |
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de> |
#
9042bf6f |
|
24-Mar-2021 |
Simon Glass <sjg@chromium.org> |
clk: Update drivers to use -EINVAL At present some drivers use -ENOSUPP to indicate that an unknown or unsupported clock is used. Most use -EINVAL, indicating an invalid value, so convert everything to that. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> |
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de> |
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de> |
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de> |
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> |
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> |
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> |
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> |
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de> |
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de> |
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de> |
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> |
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de> |
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de> |
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de> |
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8d540ccb |
|
24-Feb-2020 |
Lukasz Majewski <lukma@denx.de> |
clk: imx: Add support for pllv3 enet clock This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
8cefbe98 |
|
08-Apr-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable_bit pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
61b29b82 |
|
03-Feb-2020 |
Simon Glass <sjg@chromium.org> |
dm: core: Require users of devres to include the header At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
041b06a7 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d37ecaba |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate() Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
3391e777 |
|
17-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate() Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
efadf790 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add support for PLLV3_AV type Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
d0ceb935 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add PLLV3_SYS support Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
9841fee5 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add set_rate() support Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
cbb20014 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add disable() support Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
f4b70942 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: add enable() support Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
|
#
4abd8076 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USB div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
16faa599 |
|
10-Jan-2020 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocks Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
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#
1d7993d1 |
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24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
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#
1d7993d1 |
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24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
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#
1d7993d1 |
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24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
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#
1d7993d1 |
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24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
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#
1d7993d1 |
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24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
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#
1d7993d1 |
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24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
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#
1d7993d1 |
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24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
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#
1d7993d1 |
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24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
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#
1d7993d1 |
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24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
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#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
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#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
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#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
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#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
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#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
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#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
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#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
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#
1d7993d1 |
|
24-Jun-2019 |
Lukasz Majewski <lukma@denx.de> |
clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12) This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
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