/u-boot/drivers/ddr/microchip/ |
H A D | Makefile | 4 obj-$(CONFIG_MACH_PIC32) += ddr2.o
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/u-boot/board/atmel/at91sam9n12ek/ |
H A D | at91sam9n12ek.c | 138 static void ddr2_conf(struct atmel_mpddrc_config *ddr2) argument 140 ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); 142 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | 148 ddr2->rtr = 0x411; 150 ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET | 159 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | 164 ddr2->tpr2 = (2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET | 174 struct atmel_mpddrc_config ddr2; local 177 ddr2_conf(&ddr2); 191 ddr2_init(ATMEL_BASE_DDRSDRC, ATMEL_BASE_CS1, &ddr2); [all...] |
/u-boot/board/atmel/sama5d3_xplained/ |
H A D | sama5d3_xplained.c | 139 static void ddr2_conf(struct atmel_mpddrc_config *ddr2) argument 141 ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); 143 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | 155 ddr2->rtr = 0x411; 157 ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET | 166 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | 171 ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET | 180 struct atmel_mpddrc_config ddr2; local 182 ddr2_conf(&ddr2); 189 ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2); [all...] |
/u-boot/board/atmel/at91sam9m10g45ek/ |
H A D | at91sam9m10g45ek.c | 97 static void ddr2_conf(struct atmel_mpddrc_config *ddr2) argument 99 ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); 101 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | 106 ddr2->rtr = 0x24b; 108 ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |/* 6*7.5 = 45 ns */ 117 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | /* 2*7.5 = 15 ns */ 122 ddr2->tpr2 = (1 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET | 130 struct atmel_mpddrc_config ddr2; local 132 ddr2_conf(&ddr2); 137 ddr2_init(ATMEL_BASE_DDRSDRC0, ATMEL_BASE_CS6, &ddr2); [all...] |
/u-boot/board/gardena/smart-gateway-at91sam/ |
H A D | spl.c | 80 static void ddr2_conf(struct atmel_mpddrc_config *ddr2) argument 82 ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); 84 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | 90 ddr2->rtr = 0x411; 92 ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET | 101 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | 106 ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET | 117 struct atmel_mpddrc_config ddr2; local 120 ddr2_conf(&ddr2); 134 ddr2_init(ATMEL_BASE_DDRSDRC, ATMEL_BASE_CS1, &ddr2); [all...] |
/u-boot/board/atmel/sama5d4ek/ |
H A D | sama5d4ek.c | 138 static void ddr2_conf(struct atmel_mpddrc_config *ddr2) argument 140 ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); 142 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | 149 ddr2->rtr = 0x2b0; 151 ddr2->tpr0 = (8 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET | 160 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | 165 ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET | 174 struct atmel_mpddrc_config ddr2; local 178 ddr2_conf(&ddr2); 198 ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2); [all...] |
/u-boot/board/atmel/sama5d4_xplained/ |
H A D | sama5d4_xplained.c | 152 static void ddr2_conf(struct atmel_mpddrc_config *ddr2) argument 154 ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); 156 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | 164 ddr2->rtr = 0x2b0; 166 ddr2->tpr0 = (8 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET | 175 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | 180 ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET | 189 struct atmel_mpddrc_config ddr2; local 191 ddr2_conf(&ddr2); 198 ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2); [all...] |
/u-boot/board/atmel/at91sam9x5ek/ |
H A D | at91sam9x5ek.c | 151 static void ddr2_conf(struct atmel_mpddrc_config *ddr2) argument 153 ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); 155 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | 161 ddr2->rtr = 0x411; 163 ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET | 172 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | 177 ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET | 188 struct atmel_mpddrc_config ddr2; local 191 ddr2_conf(&ddr2); 205 ddr2_init(ATMEL_BASE_DDRSDRC, ATMEL_BASE_CS1, &ddr2); [all...] |
/u-boot/board/siemens/corvus/ |
H A D | board.c | 159 static void ddr2_conf(struct atmel_mpddrc_config *ddr2) argument 161 ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); 163 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | 168 ddr2->rtr = 0x24b; 170 ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |/* 6*7.5 = 45 ns */ 179 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | /* 2*7.5 = 15 ns */ 184 ddr2->tpr2 = (1 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET | 192 struct atmel_mpddrc_config ddr2; local 194 ddr2_conf(&ddr2); 199 ddr2_init(ATMEL_BASE_DDRSDRC0, ATMEL_BASE_CS6, &ddr2); [all...] |
/u-boot/board/atmel/sama5d3xek/ |
H A D | sama5d3xek.c | 205 static void ddr2_conf(struct atmel_mpddrc_config *ddr2) argument 207 ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); 209 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | 221 ddr2->rtr = 0x411; 223 ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET | 232 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | 237 ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET | 246 struct atmel_mpddrc_config ddr2; local 248 ddr2_conf(&ddr2); 255 ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2); [all...] |
/u-boot/arch/mips/mach-octeon/include/mach/ |
H A D | cvmx-lmcx-defs.h | 1087 uint64_t ddr2:1; member in struct:cvmx_lmcx_ddr2_ctl::cvmx_lmcx_ddr2_ctl_s 1107 uint64_t ddr2:1; member in struct:cvmx_lmcx_ddr2_ctl::cvmx_lmcx_ddr2_ctl_cn30xx
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