1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * (C) Copyright 2013 Atmel Corporation
4 * Josh Wu <josh.wu@atmel.com>
5 */
6
7#include <common.h>
8#include <init.h>
9#include <net.h>
10#include <vsprintf.h>
11#include <asm/global_data.h>
12#include <asm/io.h>
13#include <asm/arch/at91sam9x5_matrix.h>
14#include <asm/arch/at91sam9_smc.h>
15#include <asm/arch/at91_common.h>
16#include <asm/arch/at91_rstc.h>
17#include <asm/arch/at91_pio.h>
18#include <asm/arch/clk.h>
19#include <debug_uart.h>
20#include <atmel_hlcdc.h>
21#include <netdev.h>
22
23DECLARE_GLOBAL_DATA_PTR;
24
25/* ------------------------------------------------------------------------- */
26/*
27 * Miscelaneous platform dependent initialisations
28 */
29#ifdef CONFIG_NAND_ATMEL
30static void at91sam9n12ek_nand_hw_init(void)
31{
32	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
33	struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
34	unsigned long csa;
35
36	/* Assign CS3 to NAND/SmartMedia Interface */
37	csa = readl(&matrix->ebicsa);
38	csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA;
39	/* Configure databus */
40	csa &= ~AT91_MATRIX_NFD0_ON_D16; /* nandflash connect to D0~D15 */
41	/* Configure IO drive */
42	csa |= AT91_MATRIX_EBI_EBI_IOSR_NORMAL;
43
44	writel(csa, &matrix->ebicsa);
45
46	/* Configure SMC CS3 for NAND/SmartMedia */
47	writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
48		AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
49		&smc->cs[3].setup);
50	writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) |
51		AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(6),
52		&smc->cs[3].pulse);
53	writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(7),
54		&smc->cs[3].cycle);
55	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
56		AT91_SMC_MODE_EXNW_DISABLE |
57#ifdef CONFIG_SYS_NAND_DBW_16
58		AT91_SMC_MODE_DBW_16 |
59#else /* CONFIG_SYS_NAND_DBW_8 */
60		AT91_SMC_MODE_DBW_8 |
61#endif
62		AT91_SMC_MODE_TDF_CYCLE(1),
63		&smc->cs[3].mode);
64
65	/* Configure RDY/BSY pin */
66	at91_set_pio_input(AT91_PIO_PORTD, 5, 1);
67
68	/* Configure ENABLE pin for NandFlash */
69	at91_set_pio_output(AT91_PIO_PORTD, 4, 1);
70
71	at91_pio3_set_a_periph(AT91_PIO_PORTD, 0, 1);    /* NAND OE */
72	at91_pio3_set_a_periph(AT91_PIO_PORTD, 1, 1);    /* NAND WE */
73	at91_pio3_set_a_periph(AT91_PIO_PORTD, 2, 1);    /* ALE */
74	at91_pio3_set_a_periph(AT91_PIO_PORTD, 3, 1);    /* CLE */
75}
76#endif
77
78#ifdef CONFIG_USB_ATMEL
79void at91sam9n12ek_usb_hw_init(void)
80{
81	at91_set_pio_output(AT91_PIO_PORTB, 7, 0);
82}
83#endif
84
85#ifdef CONFIG_DEBUG_UART_BOARD_INIT
86void board_debug_uart_init(void)
87{
88	at91_seriald_hw_init();
89}
90#endif
91
92#ifdef CONFIG_BOARD_EARLY_INIT_F
93int board_early_init_f(void)
94{
95	return 0;
96}
97#endif
98
99int board_init(void)
100{
101	/* adress of boot parameters */
102	gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
103
104#ifdef CONFIG_NAND_ATMEL
105	at91sam9n12ek_nand_hw_init();
106#endif
107
108#ifdef CONFIG_USB_ATMEL
109	at91sam9n12ek_usb_hw_init();
110#endif
111
112	return 0;
113}
114
115int dram_init(void)
116{
117	gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
118					CFG_SYS_SDRAM_SIZE);
119	return 0;
120}
121
122#if defined(CONFIG_SPL_BUILD)
123#include <spl.h>
124#include <nand.h>
125
126void at91_spl_board_init(void)
127{
128#ifdef CONFIG_SD_BOOT
129	at91_mci_hw_init();
130#elif CONFIG_NAND_BOOT
131	at91sam9n12ek_nand_hw_init();
132#elif CONFIG_SPI_BOOT
133	at91_spi0_hw_init(1 << 4);
134#endif
135}
136
137#include <asm/arch/atmel_mpddrc.h>
138static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
139{
140	ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
141
142	ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
143		    ATMEL_MPDDRC_CR_NR_ROW_13 |
144		    ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
145		    ATMEL_MPDDRC_CR_NB_8BANKS |
146		    ATMEL_MPDDRC_CR_DECOD_INTERLEAVED);
147
148	ddr2->rtr = 0x411;
149
150	ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
151		      2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
152		      2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
153		      8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
154		      2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
155		      2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
156		      2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
157		      2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
158
159	ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
160		      200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
161		      19 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
162		      18 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
163
164	ddr2->tpr2 = (2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
165		      3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
166		      7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
167		      2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
168}
169
170void mem_init(void)
171{
172	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
173	struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
174	struct atmel_mpddrc_config ddr2;
175	unsigned long csa;
176
177	ddr2_conf(&ddr2);
178
179	/* enable DDR2 clock */
180	writel(AT91_PMC_DDR, &pmc->scer);
181
182	/* Chip select 1 is for DDR2/SDRAM */
183	csa = readl(&matrix->ebicsa);
184	csa |= AT91_MATRIX_EBI_CS1A_SDRAMC;
185	csa &= ~AT91_MATRIX_EBI_DBPU_OFF;
186	csa |= AT91_MATRIX_EBI_DBPD_OFF;
187	csa |= AT91_MATRIX_EBI_EBI_IOSR_NORMAL;
188	writel(csa, &matrix->ebicsa);
189
190	/* DDRAM2 Controller initialize */
191	ddr2_init(ATMEL_BASE_DDRSDRC, ATMEL_BASE_CS1, &ddr2);
192}
193#endif
194