1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (C) 2014 Atmel 4 * Bo Shen <voice.shen@atmel.com> 5 */ 6 7#include <common.h> 8#include <init.h> 9#include <asm/global_data.h> 10#include <asm/io.h> 11#include <asm/arch/at91_common.h> 12#include <asm/arch/at91_rstc.h> 13#include <asm/arch/atmel_mpddrc.h> 14#include <asm/arch/gpio.h> 15#include <asm/arch/clk.h> 16#include <asm/arch/sama5d3_smc.h> 17#include <asm/arch/sama5d4.h> 18#include <debug_uart.h> 19 20DECLARE_GLOBAL_DATA_PTR; 21 22#ifdef CONFIG_NAND_ATMEL 23static void sama5d4ek_nand_hw_init(void) 24{ 25 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; 26 27 at91_periph_clk_enable(ATMEL_ID_SMC); 28 29 /* Configure SMC CS3 for NAND */ 30 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) | 31 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(1), 32 &smc->cs[3].setup); 33 writel(AT91_SMC_PULSE_NWE(2) | AT91_SMC_PULSE_NCS_WR(3) | 34 AT91_SMC_PULSE_NRD(2) | AT91_SMC_PULSE_NCS_RD(3), 35 &smc->cs[3].pulse); 36 writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5), 37 &smc->cs[3].cycle); 38 writel(AT91_SMC_TIMINGS_TCLR(2) | AT91_SMC_TIMINGS_TADL(7) | 39 AT91_SMC_TIMINGS_TAR(2) | AT91_SMC_TIMINGS_TRR(3) | 40 AT91_SMC_TIMINGS_TWB(7) | AT91_SMC_TIMINGS_RBNSEL(3)| 41 AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings); 42 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | 43 AT91_SMC_MODE_EXNW_DISABLE | 44 AT91_SMC_MODE_DBW_8 | 45 AT91_SMC_MODE_TDF_CYCLE(3), 46 &smc->cs[3].mode); 47 48 at91_pio3_set_a_periph(AT91_PIO_PORTC, 5, 0); /* D0 */ 49 at91_pio3_set_a_periph(AT91_PIO_PORTC, 6, 0); /* D1 */ 50 at91_pio3_set_a_periph(AT91_PIO_PORTC, 7, 0); /* D2 */ 51 at91_pio3_set_a_periph(AT91_PIO_PORTC, 8, 0); /* D3 */ 52 at91_pio3_set_a_periph(AT91_PIO_PORTC, 9, 0); /* D4 */ 53 at91_pio3_set_a_periph(AT91_PIO_PORTC, 10, 0); /* D5 */ 54 at91_pio3_set_a_periph(AT91_PIO_PORTC, 11, 0); /* D6 */ 55 at91_pio3_set_a_periph(AT91_PIO_PORTC, 12, 0); /* D7 */ 56 at91_pio3_set_a_periph(AT91_PIO_PORTC, 13, 0); /* RE */ 57 at91_pio3_set_a_periph(AT91_PIO_PORTC, 14, 0); /* WE */ 58 at91_pio3_set_a_periph(AT91_PIO_PORTC, 15, 1); /* NCS */ 59 at91_pio3_set_a_periph(AT91_PIO_PORTC, 16, 1); /* RDY */ 60 at91_pio3_set_a_periph(AT91_PIO_PORTC, 17, 1); /* ALE */ 61 at91_pio3_set_a_periph(AT91_PIO_PORTC, 18, 1); /* CLE */ 62} 63#endif 64 65#ifdef CONFIG_CMD_USB 66static void sama5d4ek_usb_hw_init(void) 67{ 68 at91_set_pio_output(AT91_PIO_PORTE, 11, 0); 69 at91_set_pio_output(AT91_PIO_PORTE, 12, 0); 70 at91_set_pio_output(AT91_PIO_PORTE, 10, 0); 71} 72#endif 73 74#ifdef CONFIG_BOARD_LATE_INIT 75int board_late_init(void) 76{ 77#ifdef CONFIG_VIDEO 78 at91_video_show_board_info(); 79#endif 80 return 0; 81} 82#endif 83 84#ifdef CONFIG_DEBUG_UART_BOARD_INIT 85static void sama5d4ek_serial3_hw_init(void) 86{ 87 at91_pio3_set_b_periph(AT91_PIO_PORTE, 17, 1); /* TXD3 */ 88 at91_pio3_set_b_periph(AT91_PIO_PORTE, 16, 0); /* RXD3 */ 89 90 /* Enable clock */ 91 at91_periph_clk_enable(ATMEL_ID_USART3); 92} 93 94void board_debug_uart_init(void) 95{ 96 sama5d4ek_serial3_hw_init(); 97} 98#endif 99 100#ifdef CONFIG_BOARD_EARLY_INIT_F 101int board_early_init_f(void) 102{ 103 return 0; 104} 105#endif 106 107int board_init(void) 108{ 109 /* adress of boot parameters */ 110 gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; 111 112#ifdef CONFIG_NAND_ATMEL 113 sama5d4ek_nand_hw_init(); 114#endif 115#ifdef CONFIG_CMD_USB 116 sama5d4ek_usb_hw_init(); 117#endif 118 119 return 0; 120} 121 122int dram_init(void) 123{ 124 gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, 125 CFG_SYS_SDRAM_SIZE); 126 return 0; 127} 128 129/* SPL */ 130#ifdef CONFIG_SPL_BUILD 131void spl_board_init(void) 132{ 133#if CONFIG_NAND_BOOT 134 sama5d4ek_nand_hw_init(); 135#endif 136} 137 138static void ddr2_conf(struct atmel_mpddrc_config *ddr2) 139{ 140 ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); 141 142 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | 143 ATMEL_MPDDRC_CR_NR_ROW_14 | 144 ATMEL_MPDDRC_CR_CAS_DDR_CAS3 | 145 ATMEL_MPDDRC_CR_NB_8BANKS | 146 ATMEL_MPDDRC_CR_DECOD_INTERLEAVED | 147 ATMEL_MPDDRC_CR_UNAL_SUPPORTED); 148 149 ddr2->rtr = 0x2b0; 150 151 ddr2->tpr0 = (8 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET | 152 3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET | 153 3 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | 154 10 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | 155 3 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | 156 2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | 157 2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | 158 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); 159 160 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | 161 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET | 162 25 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET | 163 23 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET); 164 165 ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET | 166 2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET | 167 3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET | 168 2 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET | 169 8 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET); 170} 171 172void mem_init(void) 173{ 174 struct atmel_mpddrc_config ddr2; 175 const struct atmel_mpddr *mpddr = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC; 176 u32 tmp; 177 178 ddr2_conf(&ddr2); 179 180 /* Enable MPDDR clock */ 181 at91_periph_clk_enable(ATMEL_ID_MPDDRC); 182 at91_system_clk_enable(AT91_PMC_DDR); 183 184 tmp = ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_ONE_CYCLE; 185 writel(tmp, &mpddr->rd_data_path); 186 187 tmp = readl(&mpddr->io_calibr); 188 tmp = (tmp & ~(ATMEL_MPDDRC_IO_CALIBR_RDIV | 189 ATMEL_MPDDRC_IO_CALIBR_TZQIO | 190 ATMEL_MPDDRC_IO_CALIBR_CALCODEP | 191 ATMEL_MPDDRC_IO_CALIBR_CALCODEN)) | 192 ATMEL_MPDDRC_IO_CALIBR_DDR2_RZQ_52 | 193 ATMEL_MPDDRC_IO_CALIBR_TZQIO_(8) | 194 ATMEL_MPDDRC_IO_CALIBR_EN_CALIB; 195 writel(tmp, &mpddr->io_calibr); 196 197 /* DDRAM2 Controller initialize */ 198 ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2); 199} 200 201void at91_pmc_init(void) 202{ 203 u32 tmp; 204 205 tmp = AT91_PMC_PLLAR_29 | 206 AT91_PMC_PLLXR_PLLCOUNT(0x3f) | 207 AT91_PMC_PLLXR_MUL(87) | 208 AT91_PMC_PLLXR_DIV(1); 209 at91_plla_init(tmp); 210 211 at91_pllicpr_init(AT91_PMC_IPLL_PLLA(0x0)); 212 213 tmp = AT91_PMC_MCKR_H32MXDIV | 214 AT91_PMC_MCKR_PLLADIV_2 | 215 AT91_PMC_MCKR_MDIV_3 | 216 AT91_PMC_MCKR_CSS_PLLA; 217 at91_mck_init(tmp); 218} 219#endif 220