/u-boot/drivers/power/regulator/ |
H A D | as3722_regulator.c | 74 u8 ctrl_reg = AS3722_LDO_CONTROL0; local 79 ctrl_reg = AS3722_LDO_CONTROL1; 83 ret = pmic_clrsetbits(pmic, ctrl_reg, !enable << ldo, enable << ldo); 96 u8 ctrl_reg = AS3722_LDO_CONTROL0; local 101 ctrl_reg = AS3722_LDO_CONTROL1; 105 ret = pmic_reg_read(pmic, ctrl_reg);
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H A D | palmas_regulator.c | 56 adr = uc_pdata->ctrl_reg; 180 adr = p->ctrl_reg; 201 adr = uc_pdata->ctrl_reg; 306 uc_pdata->ctrl_reg = palmas_ldo_ctrl[type][9]; 312 uc_pdata->ctrl_reg = palmas_ldo_ctrl[type][10]; 319 uc_pdata->ctrl_reg = palmas_ldo_ctrl[type][idx]; 379 uc_pdata->ctrl_reg = palmas_smps_ctrl[type][0]; 383 uc_pdata->ctrl_reg = palmas_smps_ctrl[type][1]; 387 uc_pdata->ctrl_reg = palmas_smps_ctrl[type][2]; 396 uc_pdata->ctrl_reg [all...] |
H A D | tps65911_regulator.c | 29 u32 adr = uc_pdata->ctrl_reg; 188 uc_pdata->ctrl_reg = tps65911_vdd_reg[0][2]; 194 uc_pdata->ctrl_reg = tps65911_vdd_reg[0][3]; 202 uc_pdata->ctrl_reg = tps65911_vdd_reg[0][idx]; 325 u32 adr = uc_pdata->ctrl_reg; 361 uc_pdata->ctrl_reg = tps65911_ldo_reg[idx];
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H A D | tps80031_regulator.c | 26 u32 adr = uc_pdata->ctrl_reg; 149 uc_pdata->ctrl_reg = tps80031_ldo_reg[CTRL][7]; 155 uc_pdata->ctrl_reg = tps80031_ldo_reg[CTRL][8]; 163 uc_pdata->ctrl_reg = tps80031_ldo_reg[CTRL][idx]; 306 uc_pdata->ctrl_reg = tps80031_smps_reg[CTRL][idx];
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H A D | max77663_regulator.c | 25 u32 adr = uc_pdata->ctrl_reg; 161 uc_pdata->ctrl_reg = max77663_sd_reg[0][idx]; 219 u32 adr = uc_pdata->ctrl_reg; 289 u32 adr = uc_pdata->ctrl_reg; 324 uc_pdata->ctrl_reg = max77663_ldo_reg[idx];
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H A D | lp873x_regulator.c | 29 adr = uc_pdata->ctrl_reg; 131 adr = uc_pdata->ctrl_reg; 232 uc_pdata->ctrl_reg = lp873x_ldo_ctrl[idx]; 286 uc_pdata->ctrl_reg = lp873x_buck_ctrl[idx];
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H A D | tps65219_regulator.c | 69 adr = uc_pdata->ctrl_reg; 147 adr = uc_pdata->ctrl_reg; 258 uc_pdata->ctrl_reg = TPS65219_ENABLE_CTRL_REG; 279 uc_pdata->ctrl_reg = TPS65219_ENABLE_CTRL_REG;
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H A D | lp87565_regulator.c | 28 adr = uc_pdata->ctrl_reg; 143 uc_pdata->ctrl_reg = lp87565_buck_ctrl1[idx];
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H A D | tps65941_regulator.c | 72 adr = uc_pdata->ctrl_reg; 332 slew = pmic_reg_read(dev->parent, uc_pdata->ctrl_reg + 1); 364 adr = uc_pdata->ctrl_reg; 571 uc_pdata->ctrl_reg = tps65941_ldo_ctrl[idx - 1]; 629 uc_pdata->ctrl_reg = tps65941_buck_ctrl[idx - 1];
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/u-boot/drivers/pinctrl/aspeed/ |
H A D | pinctrl_ast2500.c | 88 u32 *ctrl_reg; local 96 ctrl_reg = &priv->scu->pinmux_ctrl1[config->reg_num - 7]; 98 ctrl_reg = &priv->scu->pinmux_ctrl[config->reg_num - 1]; 101 setbits_le32(ctrl_reg, config->ctrl_bit_mask);
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H A D | pinctrl_ast2600.c | 569 u32 ctrl_reg = (u32)priv->scu; local 580 clrbits_le32((u32)ctrl_reg + descs->offset, descs->reg_set); 582 setbits_le32((u32)ctrl_reg + descs->offset, descs->reg_set);
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/u-boot/drivers/mmc/ |
H A D | mvebu_mmc.c | 49 u32 ctrl_reg; local 56 ctrl_reg = mvebu_mmc_read(mmc, SDIO_HOST_CTRL); 57 ctrl_reg |= SDIO_HOST_CTRL_TMOUT(SDIO_HOST_CTRL_TMOUT_MAX); 58 mvebu_mmc_write(mmc, SDIO_HOST_CTRL, ctrl_reg); 295 u32 ctrl_reg = 0; local 297 ctrl_reg = mvebu_mmc_read(mmc, SDIO_HOST_CTRL); 298 ctrl_reg &= ~SDIO_HOST_CTRL_DATA_WIDTH_4_BITS; 302 ctrl_reg |= SDIO_HOST_CTRL_DATA_WIDTH_4_BITS; 306 ctrl_reg |= SDIO_HOST_CTRL_DATA_WIDTH_1_BIT; 310 ctrl_reg | [all...] |
/u-boot/drivers/spi/ |
H A D | mxc_spi.c | 114 u32 ctrl_reg; member in struct:mxc_spi_slave 182 unsigned int ctrl_reg; local 196 ctrl_reg = MXC_CSPICTRL_CHIPSELECT(cs) | 203 ctrl_reg |= MXC_CSPICTRL_PHA; 205 ctrl_reg |= MXC_CSPICTRL_POL; 207 ctrl_reg |= MXC_CSPICTRL_SSPOL; 208 mxcs->ctrl_reg = ctrl_reg; 292 mxcs->ctrl_reg = reg_ctrl; 315 mxcs->ctrl_reg [all...] |
/u-boot/drivers/i2c/ |
H A D | sun6i_p2wi.c | 86 u8 slave_addr, u8 ctrl_reg, 92 P2WI_PM_CTRL_ADDR(ctrl_reg) | 129 int p2wi_change_to_p2wi_mode(u8 slave_addr, u8 ctrl_reg, u8 init_data) argument 133 return sun6i_p2wi_change_to_p2wi_mode(base, slave_addr, ctrl_reg, 85 sun6i_p2wi_change_to_p2wi_mode(struct sunxi_p2wi_reg *base, u8 slave_addr, u8 ctrl_reg, u8 init_data) argument
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/u-boot/board/toradex/apalis-tk1/ |
H A D | apalis-tk1.c | 159 u8 ctrl_reg = AS3722_LDO_CONTROL0; local 165 ctrl_reg = AS3722_LDO_CONTROL1; 169 err = pmic_clrsetbits(pmic, ctrl_reg, 0, 1 << ldo);
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/u-boot/arch/arm/include/asm/arch-sunxi/ |
H A D | p2wi.h | 135 int p2wi_change_to_p2wi_mode(u8 slave_addr, u8 ctrl_reg, u8 init_data);
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/u-boot/include/power/ |
H A D | regulator.h | 162 * ctrl_reg: - Control register offset used to enable/disable regulator 186 u8 ctrl_reg; member in struct:dm_regulator_uclass_plat
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/u-boot/drivers/net/ |
H A D | xilinx_emaclite.c | 198 u32 ctrl_reg = __raw_readl(®s->mdioctrl); 202 __raw_writel(ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK, ®s->mdioctrl); 226 u32 ctrl_reg = __raw_readl(®s->mdioctrl); 231 __raw_writel(ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK, ®s->mdioctrl);
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/u-boot/arch/arm/mach-omap2/ |
H A D | emif-common.c | 356 u32 rgn, rgn_start, size, ctrl_reg; local 384 ctrl_reg = (regs->emif_ecc_ctrl_reg & 387 writel(ctrl_reg, &emif->emif_ecc_ctrl_reg);
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