1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) ASPEED Technology Inc. 4 */ 5 6#include <common.h> 7#include <errno.h> 8#include <asm/arch/pinctrl.h> 9#include <asm/arch/scu_ast2600.h> 10#include <asm/io.h> 11#include <dm.h> 12#include <dm/pinctrl.h> 13#include <linux/bitops.h> 14#include <linux/err.h> 15 16/* 17 * This driver works with very simple configuration that has the same name 18 * for group and function. This way it is compatible with the Linux Kernel 19 * driver. 20 */ 21struct aspeed_sig_desc { 22 u32 offset; 23 u32 reg_set; 24 int clr; 25}; 26 27struct aspeed_group_config { 28 char *group_name; 29 int ndescs; 30 struct aspeed_sig_desc *descs; 31}; 32 33struct ast2600_pinctrl_priv { 34 struct ast2600_scu *scu; 35}; 36 37static int ast2600_pinctrl_probe(struct udevice *dev) 38{ 39 struct ast2600_pinctrl_priv *priv = dev_get_priv(dev); 40 struct udevice *clk_dev; 41 int ret = 0; 42 43 /* find SCU base address from clock device */ 44 uclass_get_device_by_driver(UCLASS_CLK, DM_DRIVER_GET(aspeed_ast2600_scu), &clk_dev); 45 46 if (ret) 47 return ret; 48 49 priv->scu = dev_read_addr_ptr(clk_dev); 50 if (IS_ERR(priv->scu)) 51 return PTR_ERR(priv->scu); 52 53 return 0; 54} 55 56static struct aspeed_sig_desc i2c1_link[] = { 57 { 0x418, GENMASK(9, 8), 1 }, 58 { 0x4B8, GENMASK(9, 8), 0 }, 59}; 60 61static struct aspeed_sig_desc i2c2_link[] = { 62 { 0x418, GENMASK(11, 10), 1 }, 63 { 0x4B8, GENMASK(11, 10), 0 }, 64}; 65 66static struct aspeed_sig_desc i2c3_link[] = { 67 { 0x418, GENMASK(13, 12), 1 }, 68 { 0x4B8, GENMASK(13, 12), 0 }, 69}; 70 71static struct aspeed_sig_desc i2c4_link[] = { 72 { 0x418, GENMASK(15, 14), 1 }, 73 { 0x4B8, GENMASK(15, 14), 0 }, 74}; 75 76static struct aspeed_sig_desc i2c5_link[] = { 77 { 0x418, GENMASK(17, 16), 0 }, 78}; 79 80static struct aspeed_sig_desc i2c6_link[] = { 81 { 0x418, GENMASK(19, 18), 0 }, 82}; 83 84static struct aspeed_sig_desc i2c7_link[] = { 85 { 0x418, GENMASK(21, 20), 0 }, 86}; 87 88static struct aspeed_sig_desc i2c8_link[] = { 89 { 0x418, GENMASK(23, 22), 0 }, 90}; 91 92static struct aspeed_sig_desc i2c9_link[] = { 93 { 0x418, GENMASK(25, 24), 0 }, 94}; 95 96static struct aspeed_sig_desc i2c10_link[] = { 97 { 0x418, GENMASK(27, 26), 0 }, 98}; 99 100static struct aspeed_sig_desc i2c11_link[] = { 101 { 0x410, GENMASK(1, 0), 1 }, 102 { 0x4B0, GENMASK(1, 0), 0 }, 103}; 104 105static struct aspeed_sig_desc i2c12_link[] = { 106 { 0x410, GENMASK(3, 2), 1 }, 107 { 0x4B0, GENMASK(3, 2), 0 }, 108}; 109 110static struct aspeed_sig_desc i2c13_link[] = { 111 { 0x410, GENMASK(5, 4), 1 }, 112 { 0x4B0, GENMASK(5, 4), 0 }, 113}; 114 115static struct aspeed_sig_desc i2c14_link[] = { 116 { 0x410, GENMASK(7, 6), 1 }, 117 { 0x4B0, GENMASK(7, 6), 0 }, 118}; 119 120static struct aspeed_sig_desc i2c15_link[] = { 121 { 0x414, GENMASK(29, 28), 1 }, 122 { 0x4B4, GENMASK(29, 28), 0 }, 123}; 124 125static struct aspeed_sig_desc i2c16_link[] = { 126 { 0x414, GENMASK(31, 30), 1 }, 127 { 0x4B4, GENMASK(31, 30), 0 }, 128}; 129 130static struct aspeed_sig_desc mac1_link[] = { 131 { 0x410, BIT(4), 0 }, 132 { 0x470, BIT(4), 1 }, 133}; 134 135static struct aspeed_sig_desc mac2_link[] = { 136 { 0x410, BIT(5), 0 }, 137 { 0x470, BIT(5), 1 }, 138}; 139 140static struct aspeed_sig_desc mac3_link[] = { 141 { 0x410, BIT(6), 0 }, 142 { 0x470, BIT(6), 1 }, 143}; 144 145static struct aspeed_sig_desc mac4_link[] = { 146 { 0x410, BIT(7), 0 }, 147 { 0x470, BIT(7), 1 }, 148}; 149 150static struct aspeed_sig_desc rgmii1[] = { 151 { 0x500, BIT(6), 0 }, 152 { 0x400, GENMASK(11, 0), 0 }, 153}; 154 155static struct aspeed_sig_desc rgmii2[] = { 156 { 0x500, BIT(7), 0 }, 157 { 0x400, GENMASK(23, 12), 0 }, 158}; 159 160static struct aspeed_sig_desc rgmii3[] = { 161 { 0x510, BIT(0), 0 }, 162 { 0x410, GENMASK(27, 16), 0 }, 163}; 164 165static struct aspeed_sig_desc rgmii4[] = { 166 { 0x510, BIT(1), 0 }, 167 { 0x410, GENMASK(31, 28), 1 }, 168 { 0x4b0, GENMASK(31, 28), 0 }, 169 { 0x474, GENMASK(7, 0), 1 }, 170 { 0x414, GENMASK(7, 0), 1 }, 171 { 0x4b4, GENMASK(7, 0), 0 }, 172}; 173 174static struct aspeed_sig_desc rmii1[] = { 175 { 0x504, BIT(6), 0 }, 176 { 0x400, GENMASK(3, 0), 0 }, 177 { 0x400, GENMASK(11, 6), 0 }, 178}; 179 180static struct aspeed_sig_desc rmii2[] = { 181 { 0x504, BIT(7), 0 }, 182 { 0x400, GENMASK(15, 12), 0 }, 183 { 0x400, GENMASK(23, 18), 0 }, 184}; 185 186static struct aspeed_sig_desc rmii3[] = { 187 { 0x514, BIT(0), 0 }, 188 { 0x410, GENMASK(27, 22), 0 }, 189 { 0x410, GENMASK(19, 16), 0 }, 190}; 191 192static struct aspeed_sig_desc rmii4[] = { 193 { 0x514, BIT(1), 0 }, 194 { 0x410, GENMASK(7, 2), 1 }, 195 { 0x410, GENMASK(31, 28), 1 }, 196 { 0x414, GENMASK(7, 2), 1 }, 197 { 0x4B0, GENMASK(31, 28), 0 }, 198 { 0x4B4, GENMASK(7, 2), 0 }, 199}; 200 201static struct aspeed_sig_desc rmii1_rclk_oe[] = { 202 { 0x340, BIT(29), 0 }, 203}; 204 205static struct aspeed_sig_desc rmii2_rclk_oe[] = { 206 { 0x340, BIT(30), 0 }, 207}; 208 209static struct aspeed_sig_desc rmii3_rclk_oe[] = { 210 { 0x350, BIT(29), 0 }, 211}; 212 213static struct aspeed_sig_desc rmii4_rclk_oe[] = { 214 { 0x350, BIT(30), 0 }, 215}; 216 217static struct aspeed_sig_desc mdio1_link[] = { 218 { 0x430, BIT(17) | BIT(16), 0 }, 219}; 220 221static struct aspeed_sig_desc mdio2_link[] = { 222 { 0x470, BIT(13) | BIT(12), 1 }, 223 { 0x410, BIT(13) | BIT(12), 0 }, 224}; 225 226static struct aspeed_sig_desc mdio3_link[] = { 227 { 0x470, BIT(1) | BIT(0), 1 }, 228 { 0x410, BIT(1) | BIT(0), 0 }, 229}; 230 231static struct aspeed_sig_desc mdio4_link[] = { 232 { 0x470, BIT(3) | BIT(2), 1 }, 233 { 0x410, BIT(3) | BIT(2), 0 }, 234}; 235 236static struct aspeed_sig_desc sdio2_link[] = { 237 { 0x414, GENMASK(23, 16), 1 }, 238 { 0x4B4, GENMASK(23, 16), 0 }, 239 { 0x450, BIT(1), 0 }, 240}; 241 242static struct aspeed_sig_desc sdio1_link[] = { 243 { 0x414, GENMASK(15, 8), 0 }, 244}; 245 246/* when sdio1 8bits, sdio2 can't use */ 247static struct aspeed_sig_desc sdio1_8bit_link[] = { 248 { 0x414, GENMASK(15, 8), 0 }, 249 { 0x4b4, GENMASK(21, 18), 0 }, 250 { 0x450, BIT(3), 0 }, 251 { 0x450, BIT(1), 1 }, 252}; 253 254static struct aspeed_sig_desc emmc_link[] = { 255 { 0x400, GENMASK(31, 24), 0 }, 256}; 257 258static struct aspeed_sig_desc emmcg8_link[] = { 259 { 0x400, GENMASK(31, 24), 0 }, 260 { 0x404, GENMASK(3, 0), 0 }, 261/* set SCU504 to clear the strap bits in SCU500 */ 262 { 0x504, BIT(3), 0 }, 263 { 0x504, BIT(5), 0 }, 264}; 265 266static struct aspeed_sig_desc fmcquad_link[] = { 267 { 0x438, GENMASK(5, 4), 0 }, 268}; 269 270static struct aspeed_sig_desc siopbi_link[] = { 271 { 0x418, BIT(6), 0 }, 272}; 273 274static struct aspeed_sig_desc siopbo_link[] = { 275 { 0x418, BIT(5), 0 }, 276}; 277 278static struct aspeed_sig_desc spi1_link[] = { 279 { 0x438, GENMASK(13, 11), 0 }, 280}; 281 282static struct aspeed_sig_desc spi1abr_link[] = { 283 { 0x438, BIT(9), 0 }, 284}; 285 286static struct aspeed_sig_desc spi1cs1_link[] = { 287 { 0x438, BIT(8), 0 }, 288}; 289 290static struct aspeed_sig_desc spi1wp_link[] = { 291 { 0x438, BIT(10), 0 }, 292}; 293 294static struct aspeed_sig_desc spi1quad_link[] = { 295 { 0x438, GENMASK(15, 14), 0 }, 296}; 297 298static struct aspeed_sig_desc spi2_link[] = { 299 { 0x434, GENMASK(29, 27) | BIT(24), 0 }, 300}; 301 302static struct aspeed_sig_desc spi2cs1_link[] = { 303 { 0x434, BIT(25), 0 }, 304}; 305 306static struct aspeed_sig_desc spi2cs2_link[] = { 307 { 0x434, BIT(26), 0 }, 308}; 309 310static struct aspeed_sig_desc spi2quad_link[] = { 311 { 0x434, GENMASK(31, 30), 0 }, 312}; 313 314static struct aspeed_sig_desc thru0_link[] = { 315 { 0x4bc, GENMASK(25, 24), 0 }, 316}; 317 318static struct aspeed_sig_desc thru1_link[] = { 319 { 0x4bc, GENMASK(27, 26), 0 }, 320}; 321 322static struct aspeed_sig_desc thru2_link[] = { 323 { 0x4bc, GENMASK(29, 28), 0 }, 324}; 325 326static struct aspeed_sig_desc thru3_link[] = { 327 { 0x4bc, GENMASK(31, 30), 0 }, 328}; 329 330static struct aspeed_sig_desc fsi1[] = { 331 { 0xd48, GENMASK(21, 20), 0 }, 332}; 333 334static struct aspeed_sig_desc fsi2[] = { 335 { 0xd48, GENMASK(23, 22), 0 }, 336}; 337 338static struct aspeed_sig_desc usb2ad_link[] = { 339 { 0x440, BIT(24), 0 }, 340 { 0x440, BIT(25), 1 }, 341}; 342 343static struct aspeed_sig_desc usb2ah_link[] = { 344 { 0x440, BIT(24), 1 }, 345 { 0x440, BIT(25), 0 }, 346}; 347 348static struct aspeed_sig_desc usb2bh_link[] = { 349 { 0x440, BIT(28), 1 }, 350 { 0x440, BIT(29), 0 }, 351}; 352 353static struct aspeed_sig_desc pcie0rc_link[] = { 354 { 0x40, BIT(21), 0 }, 355}; 356 357static struct aspeed_sig_desc pcie1rc_link[] = { 358 { 0x40, BIT(19), 0 }, /* SSPRST# output enable */ 359 { 0x500, BIT(24), 0 }, /* dedicate rc reset */ 360}; 361 362static struct aspeed_sig_desc pwm0[] = { 363 {0x41c, BIT(16), 0}, 364}; 365 366static struct aspeed_sig_desc pwm1[] = { 367 {0x41c, BIT(17), 0}, 368}; 369 370static struct aspeed_sig_desc pwm2[] = { 371 {0x41c, BIT(18), 0}, 372}; 373 374static struct aspeed_sig_desc pwm3[] = { 375 {0x41c, BIT(19), 0}, 376}; 377 378static struct aspeed_sig_desc pwm4[] = { 379 {0x41c, BIT(20), 0}, 380}; 381 382static struct aspeed_sig_desc pwm5[] = { 383 {0x41c, BIT(21), 0}, 384}; 385 386static struct aspeed_sig_desc pwm6[] = { 387 {0x41c, BIT(22), 0}, 388}; 389 390static struct aspeed_sig_desc pwm7[] = { 391 {0x41c, BIT(23), 0}, 392}; 393 394static struct aspeed_sig_desc pwm8g0[] = { 395 {0x4B4, BIT(8), 0}, 396}; 397 398static struct aspeed_sig_desc pwm8g1[] = { 399 {0x41c, BIT(24), 0}, 400}; 401 402static struct aspeed_sig_desc pwm9g0[] = { 403 {0x4B4, BIT(9), 0}, 404}; 405 406static struct aspeed_sig_desc pwm9g1[] = { 407 {0x41c, BIT(25), 0}, 408}; 409 410static struct aspeed_sig_desc pwm10g0[] = { 411 {0x4B4, BIT(10), 0}, 412}; 413 414static struct aspeed_sig_desc pwm10g1[] = { 415 {0x41c, BIT(26), 0}, 416}; 417 418static struct aspeed_sig_desc pwm11g0[] = { 419 {0x4B4, BIT(11), 0}, 420}; 421 422static struct aspeed_sig_desc pwm11g1[] = { 423 {0x41c, BIT(27), 0}, 424}; 425 426static struct aspeed_sig_desc pwm12g0[] = { 427 {0x4B4, BIT(12), 0}, 428}; 429 430static struct aspeed_sig_desc pwm12g1[] = { 431 {0x41c, BIT(28), 0}, 432}; 433 434static struct aspeed_sig_desc pwm13g0[] = { 435 {0x4B4, BIT(13), 0}, 436}; 437 438static struct aspeed_sig_desc pwm13g1[] = { 439 {0x41c, BIT(29), 0}, 440}; 441 442static struct aspeed_sig_desc pwm14g0[] = { 443 {0x4B4, BIT(14), 0}, 444}; 445 446static struct aspeed_sig_desc pwm14g1[] = { 447 {0x41c, BIT(30), 0}, 448}; 449 450static struct aspeed_sig_desc pwm15g0[] = { 451 {0x4B4, BIT(15), 0}, 452}; 453 454static struct aspeed_sig_desc pwm15g1[] = { 455 {0x41c, BIT(31), 0}, 456}; 457 458static const struct aspeed_group_config ast2600_groups[] = { 459 { "MAC1LINK", ARRAY_SIZE(mac1_link), mac1_link }, 460 { "MAC2LINK", ARRAY_SIZE(mac2_link), mac2_link }, 461 { "MAC3LINK", ARRAY_SIZE(mac3_link), mac3_link }, 462 { "MAC4LINK", ARRAY_SIZE(mac4_link), mac4_link }, 463 { "RGMII1", ARRAY_SIZE(rgmii1), rgmii1 }, 464 { "RGMII2", ARRAY_SIZE(rgmii2), rgmii2 }, 465 { "RGMII3", ARRAY_SIZE(rgmii3), rgmii3 }, 466 { "RGMII4", ARRAY_SIZE(rgmii4), rgmii4 }, 467 { "RMII1", ARRAY_SIZE(rmii1), rmii1 }, 468 { "RMII2", ARRAY_SIZE(rmii2), rmii2 }, 469 { "RMII3", ARRAY_SIZE(rmii3), rmii3 }, 470 { "RMII4", ARRAY_SIZE(rmii4), rmii4 }, 471 { "RMII1RCLK", ARRAY_SIZE(rmii1_rclk_oe), rmii1_rclk_oe }, 472 { "RMII2RCLK", ARRAY_SIZE(rmii2_rclk_oe), rmii2_rclk_oe }, 473 { "RMII3RCLK", ARRAY_SIZE(rmii3_rclk_oe), rmii3_rclk_oe }, 474 { "RMII4RCLK", ARRAY_SIZE(rmii4_rclk_oe), rmii4_rclk_oe }, 475 { "MDIO1", ARRAY_SIZE(mdio1_link), mdio1_link }, 476 { "MDIO2", ARRAY_SIZE(mdio2_link), mdio2_link }, 477 { "MDIO3", ARRAY_SIZE(mdio3_link), mdio3_link }, 478 { "MDIO4", ARRAY_SIZE(mdio4_link), mdio4_link }, 479 { "SD1", ARRAY_SIZE(sdio1_link), sdio1_link }, 480 { "SD1_8bits", ARRAY_SIZE(sdio1_8bit_link), sdio1_8bit_link }, 481 { "SD2", ARRAY_SIZE(sdio2_link), sdio2_link }, 482 { "EMMC", ARRAY_SIZE(emmc_link), emmc_link }, 483 { "EMMCG8", ARRAY_SIZE(emmcg8_link), emmcg8_link }, 484 { "FMCQUAD", ARRAY_SIZE(fmcquad_link), fmcquad_link }, 485 { "SIOPBI", ARRAY_SIZE(siopbi_link), siopbi_link }, 486 { "SIOPBO", ARRAY_SIZE(siopbo_link), siopbo_link }, 487 { "SPI1", ARRAY_SIZE(spi1_link), spi1_link }, 488 { "SPI1ABR", ARRAY_SIZE(spi1abr_link), spi1abr_link }, 489 { "SPI1CS1", ARRAY_SIZE(spi1cs1_link), spi1cs1_link }, 490 { "SPI1WP", ARRAY_SIZE(spi1wp_link), spi1wp_link }, 491 { "SPI1QUAD", ARRAY_SIZE(spi1quad_link), spi1quad_link }, 492 { "SPI2", ARRAY_SIZE(spi2_link), spi2_link }, 493 { "SPI2CS1", ARRAY_SIZE(spi2cs1_link), spi2cs1_link }, 494 { "SPI2CS2", ARRAY_SIZE(spi2cs2_link), spi2cs2_link }, 495 { "SPI2QUAD", ARRAY_SIZE(spi2quad_link), spi2quad_link }, 496 { "THRU0", ARRAY_SIZE(thru0_link), thru0_link }, 497 { "THRU1", ARRAY_SIZE(thru1_link), thru1_link }, 498 { "THRU2", ARRAY_SIZE(thru2_link), thru2_link }, 499 { "THRU3", ARRAY_SIZE(thru3_link), thru3_link }, 500 { "I2C1", ARRAY_SIZE(i2c1_link), i2c1_link }, 501 { "I2C2", ARRAY_SIZE(i2c2_link), i2c2_link }, 502 { "I2C3", ARRAY_SIZE(i2c3_link), i2c3_link }, 503 { "I2C4", ARRAY_SIZE(i2c4_link), i2c4_link }, 504 { "I2C5", ARRAY_SIZE(i2c5_link), i2c5_link }, 505 { "I2C6", ARRAY_SIZE(i2c6_link), i2c6_link }, 506 { "I2C7", ARRAY_SIZE(i2c7_link), i2c7_link }, 507 { "I2C8", ARRAY_SIZE(i2c8_link), i2c8_link }, 508 { "I2C9", ARRAY_SIZE(i2c9_link), i2c9_link }, 509 { "I2C10", ARRAY_SIZE(i2c10_link), i2c10_link }, 510 { "I2C11", ARRAY_SIZE(i2c11_link), i2c11_link }, 511 { "I2C12", ARRAY_SIZE(i2c12_link), i2c12_link }, 512 { "I2C13", ARRAY_SIZE(i2c13_link), i2c13_link }, 513 { "I2C14", ARRAY_SIZE(i2c14_link), i2c14_link }, 514 { "I2C15", ARRAY_SIZE(i2c15_link), i2c15_link }, 515 { "I2C16", ARRAY_SIZE(i2c16_link), i2c16_link }, 516 { "FSI1", ARRAY_SIZE(fsi1), fsi1 }, 517 { "FSI2", ARRAY_SIZE(fsi2), fsi2 }, 518 { "USB2AD", ARRAY_SIZE(usb2ad_link), usb2ad_link }, 519 { "USB2AH", ARRAY_SIZE(usb2ah_link), usb2ah_link }, 520 { "USB2BH", ARRAY_SIZE(usb2bh_link), usb2bh_link }, 521 { "PCIE0RC", ARRAY_SIZE(pcie0rc_link), pcie0rc_link }, 522 { "PCIE1RC", ARRAY_SIZE(pcie1rc_link), pcie1rc_link }, 523 { "PWM0", ARRAY_SIZE(pwm0), pwm0 }, 524 { "PWM1", ARRAY_SIZE(pwm1), pwm1 }, 525 { "PWM2", ARRAY_SIZE(pwm2), pwm2 }, 526 { "PWM3", ARRAY_SIZE(pwm3), pwm3 }, 527 { "PWM4", ARRAY_SIZE(pwm4), pwm4 }, 528 { "PWM5", ARRAY_SIZE(pwm5), pwm5 }, 529 { "PWM6", ARRAY_SIZE(pwm6), pwm6 }, 530 { "PWM7", ARRAY_SIZE(pwm7), pwm7 }, 531 { "PWM8G0", ARRAY_SIZE(pwm8g0), pwm8g0 }, 532 { "PWM8G1", ARRAY_SIZE(pwm8g1), pwm8g1 }, 533 { "PWM9G0", ARRAY_SIZE(pwm9g0), pwm9g0 }, 534 { "PWM9G1", ARRAY_SIZE(pwm9g1), pwm9g1 }, 535 { "PWM10G0", ARRAY_SIZE(pwm10g0), pwm10g0 }, 536 { "PWM10G1", ARRAY_SIZE(pwm10g1), pwm10g1 }, 537 { "PWM11G0", ARRAY_SIZE(pwm11g0), pwm11g0 }, 538 { "PWM11G1", ARRAY_SIZE(pwm11g1), pwm11g1 }, 539 { "PWM12G0", ARRAY_SIZE(pwm12g0), pwm12g0 }, 540 { "PWM12G1", ARRAY_SIZE(pwm12g1), pwm12g1 }, 541 { "PWM13G0", ARRAY_SIZE(pwm13g0), pwm13g0 }, 542 { "PWM13G1", ARRAY_SIZE(pwm13g1), pwm13g1 }, 543 { "PWM14G0", ARRAY_SIZE(pwm14g0), pwm14g0 }, 544 { "PWM14G1", ARRAY_SIZE(pwm14g1), pwm14g1 }, 545 { "PWM15G0", ARRAY_SIZE(pwm15g0), pwm15g0 }, 546 { "PWM15G1", ARRAY_SIZE(pwm15g1), pwm15g1 }, 547}; 548 549static int ast2600_pinctrl_get_groups_count(struct udevice *dev) 550{ 551 debug("PINCTRL: get_(functions/groups)_count\n"); 552 553 return ARRAY_SIZE(ast2600_groups); 554} 555 556static const char *ast2600_pinctrl_get_group_name(struct udevice *dev, 557 unsigned selector) 558{ 559 debug("PINCTRL: get_(function/group)_name %u\n", selector); 560 561 return ast2600_groups[selector].group_name; 562} 563 564static int ast2600_pinctrl_group_set(struct udevice *dev, unsigned selector, unsigned func_selector) 565{ 566 struct ast2600_pinctrl_priv *priv = dev_get_priv(dev); 567 const struct aspeed_group_config *config; 568 const struct aspeed_sig_desc *descs; 569 u32 ctrl_reg = (u32)priv->scu; 570 u32 i; 571 572 debug("PINCTRL: group_set <%u, %u>\n", selector, func_selector); 573 if (selector >= ARRAY_SIZE(ast2600_groups)) 574 return -EINVAL; 575 576 config = &ast2600_groups[selector]; 577 for (i = 0; i < config->ndescs; i++) { 578 descs = &config->descs[i]; 579 if (descs->clr) 580 clrbits_le32((u32)ctrl_reg + descs->offset, descs->reg_set); 581 else 582 setbits_le32((u32)ctrl_reg + descs->offset, descs->reg_set); 583 } 584 585 return 0; 586} 587 588static struct pinctrl_ops ast2600_pinctrl_ops = { 589 .set_state = pinctrl_generic_set_state, 590 .get_groups_count = ast2600_pinctrl_get_groups_count, 591 .get_group_name = ast2600_pinctrl_get_group_name, 592 .get_functions_count = ast2600_pinctrl_get_groups_count, 593 .get_function_name = ast2600_pinctrl_get_group_name, 594 .pinmux_group_set = ast2600_pinctrl_group_set, 595}; 596 597static const struct udevice_id ast2600_pinctrl_ids[] = { 598 { .compatible = "aspeed,g6-pinctrl" }, 599 { } 600}; 601 602U_BOOT_DRIVER(pinctrl_aspeed) = { 603 .name = "aspeed_ast2600_pinctrl", 604 .id = UCLASS_PINCTRL, 605 .of_match = ast2600_pinctrl_ids, 606 .priv_auto = sizeof(struct ast2600_pinctrl_priv), 607 .ops = &ast2600_pinctrl_ops, 608 .probe = ast2600_pinctrl_probe, 609}; 610