/u-boot/arch/arm/include/asm/mach-imx/ |
H A D | spi.h | 14 int board_spi_cs_gpio(unsigned bus, unsigned cs);
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/u-boot/include/linux/mfd/syscon/ |
H A D | atmel-smc.h | 18 #define ATMEL_SMC_SETUP(cs) (((cs) * 0x10)) 19 #define ATMEL_HSMC_SETUP(layout, cs) \ 20 ((layout)->timing_regs_offset + ((cs) * 0x14)) 21 #define ATMEL_SMC_PULSE(cs) (((cs) * 0x10) + 0x4) 22 #define ATMEL_HSMC_PULSE(layout, cs) \ 23 ((layout)->timing_regs_offset + ((cs) * 0x14) + 0x4) 24 #define ATMEL_SMC_CYCLE(cs) (((cs) * [all...] |
/u-boot/arch/m68k/cpu/mcf5445x/ |
H A D | dspi.c | 13 void dspi_chip_select(int cs) argument 18 switch (cs) { 35 void dspi_chip_unselect(int cs) argument 40 if (cs == 1)
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/u-boot/arch/arm/mach-omap2/omap3/ |
H A D | sdrc.c | 42 if (readl(&sdrc_base->cs[CS0].mr) == SDRC_MR_0_SDR) 51 static u32 get_sdr_cs_size(u32 cs) argument 56 size = readl(&sdrc_base->cs[cs].mcfg) >> 8; 82 * - Get offset of cs from cs0 start 84 u32 get_sdr_cs_offset(u32 cs) argument 88 if (!cs) 102 static void write_sdrc_timings(u32 cs, struct sdrc_actim *sdrc_actim_base, argument 106 writel(timings->mcfg, &sdrc_base->cs[cs] 130 do_sdrc_init(u32 cs, u32 early) argument [all...] |
H A D | spl_id_nand.c | 38 writeb(NAND_CMD_RESET, &gpmc_cfg->cs[0].nand_cmd); 39 writeb(NAND_CMD_STATUS, &gpmc_cfg->cs[0].nand_cmd); 40 while ((readl(&gpmc_cfg->cs[0].nand_dat) & NAND_STATUS_READY) 46 writeb(NAND_CMD_READID, &gpmc_cfg->cs[0].nand_cmd); 49 writeb(0x0, &gpmc_cfg->cs[0].nand_adr); 52 *mfr = readb(&gpmc_cfg->cs[0].nand_dat); 53 *id = readb(&gpmc_cfg->cs[0].nand_dat);
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/u-boot/drivers/video/ |
H A D | hitachi_tx18d42vm_lcd.c | 21 static void lcd_panel_spi_write(int cs, int clk, int mosi, argument 26 gpio_direction_output(cs, 0); 35 gpio_direction_output(cs, 1); 51 int i, cs, clk, mosi, ret = 0; local 53 cs = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_SPI_CS); 57 if (cs == -1 || clk == -1 || mosi == 1) { 62 if (gpio_request(cs, "tx18d42vm-spi-cs") != 0 || 71 lcd_panel_spi_write(cs, clk, mosi, init_data[i], 16); 75 lcd_panel_spi_write(cs, cl [all...] |
/u-boot/drivers/ddr/marvell/axp/ |
H A D | ddr3_write_leveling.c | 48 static int ddr3_write_leveling_single_cs(u32 cs, u32 freq, int ratio_2to1, 68 u32 reg, phase, delay, cs, pup; local 108 for (cs = 0; cs < MAX_CS; cs++) { 109 if (dram_info->cs_ena & (1 << cs)) { 117 ddr3_read_pup_reg(PUP_WL_MODE, cs, 123 dram_info->wl_val[cs][pup][P] = phase; 124 dram_info->wl_val[cs][pup][D] = delay; 125 dram_info->wl_val[cs][pu 188 u32 cs, cnt, pup_num, sum, phase, delay, max_pup_num, pup, sdram_offset; local 476 u32 reg, phase, delay, cs, pup, pup_num; local 661 u32 reg, cs, cnt, pup, max_pup_num; local 886 u32 reg, cs, cnt, pup; local 1126 ddr3_write_leveling_single_cs(u32 cs, u32 freq, int ratio_2to1, u32 *result, MV_DRAM_INFO *dram_info) argument [all...] |
H A D | ddr3_read_leveling.c | 45 static int ddr3_read_leveling_single_cs_rl_mode(u32 cs, u32 freq, 49 static int ddr3_read_leveling_single_cs_window_mode(u32 cs, u32 freq, 92 u32 delay, phase, pup, cs; local 98 for (cs = 0; cs < MAX_CS; cs++) { 99 if (dram_info->cs_ena & (1 << cs)) { 107 ddr3_read_pup_reg(PUP_RL_MODE, cs, 112 dram_info->rl_val[cs][pup][P] = phase; 117 dram_info->rl_val[cs][pu 182 u32 reg, cs, ecc, pup_num, phase, delay, pup; local 336 overrun(u32 cs, MV_DRAM_INFO *info, u32 pup, u32 locked_pups, u32 *locked_sum, u32 ecc, int *first_octet_locked, int *counter_in_progress, int final_delay, u32 delay, u32 phase) argument 400 ddr3_read_leveling_single_cs_rl_mode(u32 cs, u32 freq, int ratio_2to1, u32 ecc, MV_DRAM_INFO *dram_info) argument 752 ddr3_read_leveling_single_cs_window_mode(u32 cs, u32 freq, int ratio_2to1, u32 ecc, MV_DRAM_INFO *dram_info) argument [all...] |
/u-boot/drivers/memory/ |
H A D | ti-gpmc.c | 72 static void gpmc_cs_write_reg(int cs, int idx, u32 val) argument 76 reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx; 80 static u32 gpmc_cs_read_reg(int cs, int idx) argument 84 reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx; 100 * @cs: Chip Select Region. 103 * GPMC_CS_CONFIG1 GPMCFCLKDIVIDER for cs has to be setup 106 static unsigned long gpmc_get_clk_period(int cs, enum gpmc_clk_domain cd) argument 115 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1); 128 static unsigned int gpmc_ns_to_clk_ticks(unsigned int time_ns, int cs, argument 134 tick_ps = gpmc_get_clk_period(cs, c 154 gpmc_clk_ticks_to_ns(unsigned int ticks, int cs, enum gpmc_clk_domain cd) argument 160 gpmc_cs_modify_reg(int cs, int reg, u32 mask, bool value) argument 172 gpmc_cs_bool_timings(int cs, const struct gpmc_bool_timings *p) argument 214 get_gpmc_timing_reg( int cs, int reg, int st_bit, int end_bit, int max, const char *name, const enum gpmc_clk_domain cd, int shift, bool raw, bool noval) argument 276 gpmc_show_regs(int cs, const char *desc) argument 291 gpmc_cs_show_timings(int cs, const char *desc) argument 367 gpmc_cs_show_timings(int cs, const char *desc) argument 388 set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit, int max, int time, enum gpmc_clk_domain cd, const char *name) argument 480 gpmc_cs_set_timings(int cs, const struct gpmc_timings *t, const struct gpmc_settings *s) argument 632 gpmc_cs_set_memconf(int cs, resource_size_t base, u32 size) argument 659 gpmc_cs_enable_mem(int cs) argument 668 gpmc_cs_disable_mem(int cs) argument 677 gpmc_cs_set_reserved(int cs, int reserved) argument 684 gpmc_cs_reserved(int cs) argument 705 gpmc_cs_request(ofnode node, int cs, struct resource *res) argument 744 gpmc_cs_free(int cs) argument 795 gpmc_cs_program_settings(int cs, struct gpmc_settings *p) argument 866 gpmc_cs_set_name(int cs, const char *name) argument 873 gpmc_cs_get_name(int cs) argument 1011 u32 val, cs; local [all...] |
H A D | ti-aemif.c | 16 #define AEMIF_CONFIG(cs) (KS2_AEMIF_CNTRL_BASE + 0x10 + (cs * 4)) 37 static void aemif_configure(int cs, struct aemif_config *cfg) argument 43 tmp |= (1 << cs); 48 tmp |= (1 << cs); 52 tmp = __raw_readl(AEMIF_CONFIG(cs)); 65 __raw_writel(tmp, AEMIF_CONFIG(cs)); 70 int cs; local 77 for (cs = 0; cs < num_c [all...] |
/u-boot/board/freescale/ls1043ardb/ |
H A D | ddr.h | 49 .cs[0].bnds = 0x0000007F, 50 .cs[1].bnds = 0, 51 .cs[2].bnds = 0, 52 .cs[3].bnds = 0, 53 .cs[0].config = 0x80040322, 54 .cs[0].config_2 = 0, 55 .cs[1].config = 0, 56 .cs[1].config_2 = 0, 57 .cs[2].config = 0, 58 .cs[ [all...] |
/u-boot/board/kontron/sl28/ |
H A D | ddr.c | 22 .cs[0].bnds = 0x0000007f, 23 .cs[0].config = 0x80044402, 24 .cs[1].bnds = 0x008000ff, 25 .cs[1].config = 0x80004402, 70 ddr_cfg_regs.cs[1].bnds = 0; 71 ddr_cfg_regs.cs[1].config = 0; 78 ddr_cfg_regs.cs[0].bnds = 0x000000ff; 79 ddr_cfg_regs.cs[0].config = 0x80044403; 80 ddr_cfg_regs.cs[1].bnds = 0x010001ff; 81 ddr_cfg_regs.cs[ [all...] |
/u-boot/drivers/spi/ |
H A D | spi.c | 24 unsigned int cs) 35 slave->cs = cs; 23 spi_do_alloc_slave(int offset, int size, unsigned int bus, unsigned int cs) argument
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H A D | mt7620_spi.c | 63 static void mt7620_spi_master_setup(struct mt7620_spi *ms, int cs) argument 103 writel(cfg, &ms->m[cs]->cfg); 105 writel(SPI_HIGH, &ms->m[cs]->ctl); 108 static void mt7620_spi_set_cs(struct mt7620_spi *ms, int cs, bool enable) argument 111 mt7620_spi_master_setup(ms, cs); 117 clrbits_32(&ms->m[cs]->ctl, SPI_HIGH); 119 setbits_32(&ms->m[cs]->ctl, SPI_HIGH); 144 static inline int mt7620_spi_busy_poll(struct mt7620_spi *ms, int cs) argument 148 return readl_poll_timeout(&ms->m[cs]->stat, val, !(val & SPI_BUSY), 152 static int mt7620_spi_read(struct mt7620_spi *ms, int cs, u argument 171 mt7620_spi_write(struct mt7620_spi *ms, int cs, const u8 *buf, size_t len) argument 196 int cs, ret = 0; local [all...] |
H A D | spi-aspeed-smc.c | 87 void (*set_4byte)(struct udevice *bus, u32 cs); 96 u32 cs; member in struct:aspeed_spi_decoded_range 153 static void ast2400_fmc_chip_set_4byte(struct udevice *bus, u32 cs) argument 159 reg_val |= 0x1 << cs; 163 static void ast2400_spi_chip_set_4byte(struct udevice *bus, u32 cs) argument 166 struct aspeed_spi_flash *flash = &priv->flashes[cs]; 196 priv->flashes[slave_plat->cs].max_freq = hclk_clk / (i + 1); 204 i + 1, hclk_masks[i], priv->flashes[slave_plat->cs].max_freq); 241 static void ast2500_spi_chip_set_4byte(struct udevice *bus, u32 cs) argument 247 reg_val |= 0x1 << cs; 264 int cs; local 381 ast2600_spi_chip_set_4byte(struct udevice *bus, u32 cs) argument 398 int cs; local 492 int cs = plat->max_cs - 1; local 592 u32 cs = slave_plat->cs; local 672 u32 cs = slave_plat->cs; local 729 u32 cs = slave_plat->cs; local 754 u32 cs = slave_plat->cs; local 768 u32 cs; local 788 u32 cs; local 826 u32 cs; local 931 u32 cs; local [all...] |
/u-boot/arch/arm/include/asm/arch-mx31/ |
H A D | sys_proto.h | 18 void mxc_setup_weimcs(int cs, const struct mxc_weimcs *weimcs);
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/u-boot/board/compulab/common/ |
H A D | common.h | 27 int cl_omap3_smc911x_init(int id, int cs, u32 base_addr, 30 static inline int cl_omap3_smc911x_init(int id, int cs, u32 base_addr, argument
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H A D | omap3_smc911x.c | 31 static void cl_omap3_smc911x_setup_net_chip_gmpc(int cs, u32 base_addr) argument 36 &gpmc_cfg->cs[cs], base_addr, GPMC_SIZE_16M); 75 int cl_omap3_smc911x_init(int id, int cs, u32 base_addr, argument 80 cl_omap3_smc911x_setup_net_chip_gmpc(cs, base_addr);
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/u-boot/drivers/ddr/fsl/ |
H A D | mpc85xx_ddr_gen1.c | 30 out_be32(&ddr->cs0_bnds, regs->cs[i].bnds); 31 out_be32(&ddr->cs0_config, regs->cs[i].config); 34 out_be32(&ddr->cs1_bnds, regs->cs[i].bnds); 35 out_be32(&ddr->cs1_config, regs->cs[i].config); 38 out_be32(&ddr->cs2_bnds, regs->cs[i].bnds); 39 out_be32(&ddr->cs2_config, regs->cs[i].config); 42 out_be32(&ddr->cs3_bnds, regs->cs[i].bnds); 43 out_be32(&ddr->cs3_config, regs->cs[i].config);
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/u-boot/board/mscc/common/ |
H A D | spi.c | 13 u32 cs = spi_chip_select(dev); local 21 ICPU_SW_MODE_SW_SPI_CS(BIT(cs)),
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/u-boot/board/atmel/at91sam9261ek/ |
H A D | at91sam9261ek.c | 52 &smc->cs[3].setup); 55 &smc->cs[3].pulse); 57 &smc->cs[3].cycle); 61 &smc->cs[3].setup); 64 &smc->cs[3].pulse); 66 &smc->cs[3].cycle); 76 &smc->cs[3].mode); 100 &smc->cs[2].setup); 103 &smc->cs[2].pulse); 105 &smc->cs[ [all...] |
/u-boot/drivers/mfd/ |
H A D | atmel-smc.c | 243 * @cs: the CS id 249 void atmel_smc_cs_conf_apply(struct regmap *regmap, int cs, argument 252 regmap_write(regmap, ATMEL_SMC_SETUP(cs), conf->setup); 253 regmap_write(regmap, ATMEL_SMC_PULSE(cs), conf->pulse); 254 regmap_write(regmap, ATMEL_SMC_CYCLE(cs), conf->cycle); 255 regmap_write(regmap, ATMEL_SMC_MODE(cs), conf->mode); 262 * @cs: the CS id 271 int cs, const struct atmel_smc_cs_conf *conf) 273 regmap_write(regmap, ATMEL_HSMC_SETUP(layout, cs), conf->setup); 274 regmap_write(regmap, ATMEL_HSMC_PULSE(layout, cs), con 269 atmel_hsmc_cs_conf_apply(struct regmap *regmap, const struct atmel_hsmc_reg_layout *layout, int cs, const struct atmel_smc_cs_conf *conf) argument 290 atmel_smc_cs_conf_get(struct regmap *regmap, int cs, struct atmel_smc_cs_conf *conf) argument 310 atmel_hsmc_cs_conf_get(struct regmap *regmap, const struct atmel_hsmc_reg_layout *layout, int cs, struct atmel_smc_cs_conf *conf) argument [all...] |
/u-boot/arch/arm/mach-omap2/ |
H A D | mem-common.c | 46 u32 mem_ok(u32 cs) argument 51 addr = OMAP34XX_SDRC_CS0 + get_sdr_cs_offset(cs); 67 void enable_gpmc_cs_config(const u32 *gpmc_config, const struct gpmc_cs *cs, argument 70 writel(0, &cs->config7); 73 writel(gpmc_config[0], &cs->config1); 74 writel(gpmc_config[1], &cs->config2); 75 writel(gpmc_config[2], &cs->config3); 76 writel(gpmc_config[3], &cs->config4); 77 writel(gpmc_config[4], &cs->config5); 78 writel(gpmc_config[5], &cs [all...] |
/u-boot/cmd/ |
H A D | spi.c | 29 static unsigned int cs; variable 36 static int do_spi_xfer(int bus, int cs) argument 45 snprintf(name, sizeof(name), "generic_%d:%d", bus, cs); 49 ret = _spi_get_bus_and_cs(bus, cs, freq, mode, "spi_generic_drv", 54 slave = spi_setup_slave(bus, cs, freq, mode); 56 printf("Invalid device %d:%d\n", bus, cs); 122 cs = dectoul(cp + 1, &cp); 124 cs = bus; 159 if (do_spi_xfer(bus, cs)) 170 "[<bus>:]<cs>[ [all...] |
/u-boot/drivers/ddr/marvell/a38x/ |
H A D | mv_ddr_regs.h | 118 #define CS_STRUCT_OFFS(cs) (CS_STRUCT_BASE + (cs) * 4) 121 #define CS_SIZE_OFFS(cs) (CS_SIZE_BASE + (cs) * 4) 124 #define CS_SIZE_HIGH_OFFS(cs) (CS_SIZE_HIGH_BASE + (cs)) 135 #define SDRAM_OP_CMD_CS_OFFS(cs) (SDRAM_OP_CMD_CS_BASE + (cs)) 231 #define RD_SMPL_DLY_CS_OFFS(cs) (RD_SMPL_DLY_CS_BASE + (cs) * [all...] |