Searched refs:clock_rate (Results 1 - 25 of 38) sorted by relevance

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/u-boot/arch/x86/cpu/slimbootloader/
H A Dslimbootloader.c16 * This sets tsc_base and clock_rate for early_timer and tsc_timer.
22 * Configuring tsc_base and clock_rate here makes x86 tsc_timer driver
43 gd->arch.clock_rate = data->frequency * 1000;
44 debug("freq=0x%lx\n", gd->arch.clock_rate);
/u-boot/drivers/timer/
H A Dtimer-uclass.c49 return uc_priv->clock_rate;
70 uc_priv->clock_rate = ret;
75 uc_priv->clock_rate = dev_read_u32_default(dev, "clock-frequency", 0);
85 if (!uc_priv->clock_rate)
99 if (uc_priv->clock_rate)
112 uc_priv->clock_rate = cpu_plat->timebase_freq;
H A Dsandbox_timer.c44 else if (!uc_priv->clock_rate)
45 uc_priv->clock_rate = SANDBOX_TIMER_RATE;
H A Dnomadik-mtu-timer.c77 if (!uc_priv->clock_rate)
81 if (uc_priv->clock_rate > 32000000) {
82 uc_priv->clock_rate /= 16;
H A Domap-timer.c62 if (!uc_priv->clock_rate)
63 uc_priv->clock_rate = V_SCLK;
65 uc_priv->clock_rate /= (2 << SYS_PTV);
H A Dtsc_timer.c404 if (!gd->arch.clock_rate) {
437 gd->arch.clock_rate = CONFIG_X86_TSC_TIMER_FREQ;
442 if (!gd->arch.clock_rate)
443 gd->arch.clock_rate = fast_calibrate * 1000000;
454 if (!gd->arch.clock_rate) {
459 if (!uc_priv->clock_rate)
462 uc_priv->clock_rate = gd->arch.clock_rate;
477 return gd->arch.clock_rate;
H A Darm_global_timer.c60 uc_priv->clock_rate = ret;
62 uc_priv->clock_rate = CFG_SYS_HZ_CLOCK;
H A Dgxp-timer.c42 uc_priv->clock_rate = 1000000;
H A Dostm_timer.c51 uc_priv->clock_rate = clk_get_rate(&clk);
53 uc_priv->clock_rate = get_board_sys_clk() / 2;
H A Ddw-apb-timer.c63 uc_priv->clock_rate = dtplat->clock_frequency;
76 uc_priv->clock_rate = clk_get_rate(&clk);
H A Dorion-timer.c123 uc_priv->clock_rate = MVEBU_TIMER_FIXED_RATE_25MHZ;
125 uc_priv->clock_rate = CFG_SYS_TCLK;
H A Dmtk_timer.c83 uc_priv->clock_rate = clk_get_rate(&clk);
84 if (!uc_priv->clock_rate)
H A Datmel_pit_timer.c54 uc_priv->clock_rate = clk_rate / 16;
H A Dast_timer.c49 uc_priv->clock_rate = AST_TMC_RATE;
H A Driscv_timer.c92 uc_priv->clock_rate = rate;
H A Dtegra-timer.c50 * need of using adjusments involving uc_priv->clock_rate.
64 uc_priv->clock_rate = TEGRA_TIMER_RATE;
H A Dmchp-pit64b-timer.c74 uc_priv->clock_rate = rate / 16;
H A Dnpcm-timer.c72 uc_priv->clock_rate = NPCM_TIMER_CLOCK_RATE;
/u-boot/include/
H A Dtimer.h90 * @clock_rate: the timer input clock frequency in Hz
93 unsigned long clock_rate; member in struct:timer_dev_priv
112 * for tracing. This corresponds to the clock_rate value in struct
/u-boot/arch/x86/lib/
H A Dbdinfo.c20 bdinfo_print_num_l("clock_rate", gd->arch.clock_rate);
/u-boot/drivers/i2c/
H A Dimx_lpi2c.c281 u32 clock_rate; local
286 clock_rate = clk_get_rate(&i2c_bus->per_clk);
287 if (clock_rate <= 0) {
288 dev_err(bus, "Failed to get i2c clk: %d\n", clock_rate);
289 return clock_rate;
292 clock_rate = imx_get_i2cclk(dev_seq(bus));
293 if (!clock_rate)
306 rate = (clock_rate / preescale) / (1 + 3 + 2 + 2 / preescale);
308 rate = (clock_rate / preescale / (3 * clkhi + 2 + 2 / preescale));
/u-boot/arch/arm/mach-bcm283x/
H A Dmsg.c84 u32 clock_rate = 0; local
100 clock_rate = msg_clk->get_clock_rate.body.resp.rate_hz;
102 if (clock_rate == 0) {
113 clock_rate = msg_clk->get_clock_rate.body.resp.rate_hz;
116 return clock_rate;
/u-boot/drivers/usb/host/
H A Ddwc3-octeon-glue.c152 u32 clock_rate; local
160 i = dev_read_u32(dev, "refclk-frequency", &clock_rate);
203 clock_rate != CLOCK_100MHZ)
204 printf("Invalid UCTL clock rate of %u\n", clock_rate);
255 switch (clock_rate) {
258 clock_rate);
/u-boot/drivers/serial/
H A Dserial_stm32.h54 unsigned long int clock_rate; member in struct:stm32x7_serial_plat
H A Dserial_stm32.c35 u32 clock_rate,
45 int_div = DIV_ROUND_CLOSEST(clock_rate, baudrate);
68 plat->clock_rate, baudrate);
232 plat->clock_rate = clk_get_rate(&clk);
233 if (!plat->clock_rate) {
33 _stm32_serial_setbrg(void __iomem *base, struct stm32_uart_info *uart_info, u32 clock_rate, int baudrate) argument

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