1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Octeon family DWC3 specific glue layer 4 * 5 * Copyright (C) 2020 Stefan Roese <sr@denx.de> 6 * 7 * The low-level init code is based on the Linux driver octeon-usb.c by 8 * David Daney <david.daney@cavium.com>, which is: 9 * Copyright (C) 2010-2017 Cavium Networks 10 */ 11 12#include <dm.h> 13#include <errno.h> 14#include <usb.h> 15#include <asm/global_data.h> 16#include <asm/io.h> 17#include <dm/device_compat.h> 18#include <dm/lists.h> 19#include <dm/of_access.h> 20#include <linux/bitfield.h> 21#include <linux/delay.h> 22#include <linux/err.h> 23#include <linux/io.h> 24#include <linux/usb/dwc3.h> 25#include <linux/usb/otg.h> 26#include <mach/octeon-model.h> 27 28DECLARE_GLOBAL_DATA_PTR; 29 30#define CVMX_GPIO_BIT_CFGX(i) (0x0001070000000900ull + ((i) * 8)) 31#define CVMX_GPIO_XBIT_CFGX(i) (0x0001070000000900ull + \ 32 ((i) & 31) * 8 - 8 * 16) 33 34#define GPIO_BIT_CFG_TX_OE BIT_ULL(0) 35#define GPIO_BIT_CFG_OUTPUT_SEL GENMASK_ULL(20, 16) 36 37#define UCTL_CTL_UCTL_RST BIT_ULL(0) 38#define UCTL_CTL_UAHC_RST BIT_ULL(1) 39#define UCTL_CTL_UPHY_RST BIT_ULL(2) 40#define UCTL_CTL_DRD_MODE BIT_ULL(3) 41#define UCTL_CTL_SCLK_EN BIT_ULL(4) 42#define UCTL_CTL_HS_POWER_EN BIT_ULL(12) 43#define UCTL_CTL_SS_POWER_EN BIT_ULL(14) 44#define UCTL_CTL_H_CLKDIV_SEL GENMASK_ULL(26, 24) 45#define UCTL_CTL_H_CLKDIV_RST BIT_ULL(28) 46#define UCTL_CTL_H_CLK_EN BIT_ULL(30) 47#define UCTL_CTL_REF_CLK_FSEL GENMASK_ULL(37, 32) 48#define UCTL_CTL_REF_CLK_DIV2 BIT_ULL(38) 49#define UCTL_CTL_REF_SSP_EN BIT_ULL(39) 50#define UCTL_CTL_MPLL_MULTIPLIER GENMASK_ULL(46, 40) 51#define UCTL_CTL_SSC_EN BIT_ULL(59) 52#define UCTL_CTL_REF_CLK_SEL GENMASK_ULL(61, 60) 53 54#define UCTL_HOST_CFG 0xe0 55#define UCTL_HOST_CFG_PPC_ACTIVE_HIGH_EN BIT_ULL(24) 56#define UCTL_HOST_CFG_PPC_EN BIT_ULL(25) 57 58#define UCTL_SHIM_CFG 0xe8 59#define UCTL_SHIM_CFG_CSR_ENDIAN_MODE GENMASK_ULL(1, 0) 60#define UCTL_SHIM_CFG_DMA_ENDIAN_MODE GENMASK_ULL(9, 8) 61 62#define OCTEON_H_CLKDIV_SEL 8 63#define OCTEON_MIN_H_CLK_RATE 150000000 64#define OCTEON_MAX_H_CLK_RATE 300000000 65 66#define CLOCK_50MHZ 50000000 67#define CLOCK_100MHZ 100000000 68#define CLOCK_125MHZ 125000000 69 70static u8 clk_div[OCTEON_H_CLKDIV_SEL] = {1, 2, 4, 6, 8, 16, 24, 32}; 71 72static int dwc3_octeon_config_power(struct udevice *dev, void __iomem *base) 73{ 74 u64 uctl_host_cfg; 75 u64 gpio_bit; 76 u32 gpio_pwr[3]; 77 int gpio, len, power_active_low; 78 const struct device_node *node = dev_np(dev); 79 int index = ((u64)base >> 24) & 1; 80 void __iomem *gpio_bit_cfg; 81 82 if (of_find_property(node, "power", &len)) { 83 if (len == 12) { 84 dev_read_u32_array(dev, "power", gpio_pwr, 3); 85 power_active_low = gpio_pwr[2] & 0x01; 86 gpio = gpio_pwr[1]; 87 } else if (len == 8) { 88 dev_read_u32_array(dev, "power", gpio_pwr, 2); 89 power_active_low = 0; 90 gpio = gpio_pwr[1]; 91 } else { 92 printf("dwc3 controller clock init failure\n"); 93 return -EINVAL; 94 } 95 96 gpio_bit_cfg = ioremap(CVMX_GPIO_BIT_CFGX(gpio), 0); 97 98 if ((OCTEON_IS_MODEL(OCTEON_CN73XX) || 99 OCTEON_IS_MODEL(OCTEON_CNF75XX)) && gpio <= 31) { 100 gpio_bit = ioread64(gpio_bit_cfg); 101 gpio_bit |= GPIO_BIT_CFG_TX_OE; 102 gpio_bit &= ~GPIO_BIT_CFG_OUTPUT_SEL; 103 gpio_bit |= FIELD_PREP(GPIO_BIT_CFG_OUTPUT_SEL, 104 index == 0 ? 0x14 : 0x15); 105 iowrite64(gpio_bit, gpio_bit_cfg); 106 } else if (gpio <= 15) { 107 gpio_bit = ioread64(gpio_bit_cfg); 108 gpio_bit |= GPIO_BIT_CFG_TX_OE; 109 gpio_bit &= ~GPIO_BIT_CFG_OUTPUT_SEL; 110 gpio_bit |= FIELD_PREP(GPIO_BIT_CFG_OUTPUT_SEL, 111 index == 0 ? 0x14 : 0x19); 112 iowrite64(gpio_bit, gpio_bit_cfg); 113 } else { 114 gpio_bit_cfg = ioremap(CVMX_GPIO_XBIT_CFGX(gpio), 0); 115 116 gpio_bit = ioread64(gpio_bit_cfg); 117 gpio_bit |= GPIO_BIT_CFG_TX_OE; 118 gpio_bit &= ~GPIO_BIT_CFG_OUTPUT_SEL; 119 gpio_bit |= FIELD_PREP(GPIO_BIT_CFG_OUTPUT_SEL, 120 index == 0 ? 0x14 : 0x19); 121 iowrite64(gpio_bit, gpio_bit_cfg); 122 } 123 124 /* Enable XHCI power control and set if active high or low. */ 125 uctl_host_cfg = ioread64(base + UCTL_HOST_CFG); 126 uctl_host_cfg |= UCTL_HOST_CFG_PPC_EN; 127 if (power_active_low) 128 uctl_host_cfg &= ~UCTL_HOST_CFG_PPC_ACTIVE_HIGH_EN; 129 else 130 uctl_host_cfg |= UCTL_HOST_CFG_PPC_ACTIVE_HIGH_EN; 131 iowrite64(uctl_host_cfg, base + UCTL_HOST_CFG); 132 133 /* Wait for power to stabilize */ 134 mdelay(10); 135 } else { 136 /* Disable XHCI power control and set if active high. */ 137 uctl_host_cfg = ioread64(base + UCTL_HOST_CFG); 138 uctl_host_cfg &= ~UCTL_HOST_CFG_PPC_EN; 139 uctl_host_cfg &= ~UCTL_HOST_CFG_PPC_ACTIVE_HIGH_EN; 140 iowrite64(uctl_host_cfg, base + UCTL_HOST_CFG); 141 dev_warn(dev, "dwc3 controller clock init failure.\n"); 142 } 143 144 return 0; 145} 146 147static int dwc3_octeon_clocks_start(struct udevice *dev, void __iomem *base) 148{ 149 u64 uctl_ctl; 150 int ref_clk_sel = 2; 151 u64 div; 152 u32 clock_rate; 153 int mpll_mul; 154 int i; 155 u64 h_clk_rate; 156 void __iomem *uctl_ctl_reg = base; 157 const char *ss_clock_type; 158 const char *hs_clock_type; 159 160 i = dev_read_u32(dev, "refclk-frequency", &clock_rate); 161 if (i) { 162 printf("No UCTL \"refclk-frequency\"\n"); 163 return -EINVAL; 164 } 165 166 ss_clock_type = dev_read_string(dev, "refclk-type-ss"); 167 if (!ss_clock_type) { 168 printf("No UCTL \"refclk-type-ss\"\n"); 169 return -EINVAL; 170 } 171 172 hs_clock_type = dev_read_string(dev, "refclk-type-hs"); 173 if (!hs_clock_type) { 174 printf("No UCTL \"refclk-type-hs\"\n"); 175 return -EINVAL; 176 } 177 178 if (strcmp("dlmc_ref_clk0", ss_clock_type) == 0) { 179 if (strcmp(hs_clock_type, "dlmc_ref_clk0") == 0) { 180 ref_clk_sel = 0; 181 } else if (strcmp(hs_clock_type, "pll_ref_clk") == 0) { 182 ref_clk_sel = 2; 183 } else { 184 printf("Invalid HS clock type %s, using pll_ref_clk\n", 185 hs_clock_type); 186 } 187 } else if (strcmp(ss_clock_type, "dlmc_ref_clk1") == 0) { 188 if (strcmp(hs_clock_type, "dlmc_ref_clk1") == 0) { 189 ref_clk_sel = 1; 190 } else if (strcmp(hs_clock_type, "pll_ref_clk") == 0) { 191 ref_clk_sel = 3; 192 } else { 193 printf("Invalid HS clock type %s, using pll_ref_clk\n", 194 hs_clock_type); 195 ref_clk_sel = 3; 196 } 197 } else { 198 printf("Invalid SS clock type %s, using dlmc_ref_clk0\n", 199 ss_clock_type); 200 } 201 202 if ((ref_clk_sel == 0 || ref_clk_sel == 1) && 203 clock_rate != CLOCK_100MHZ) 204 printf("Invalid UCTL clock rate of %u\n", clock_rate); 205 206 /* 207 * Step 1: Wait for all voltages to be stable...that surely 208 * happened before this driver is started. SKIP 209 */ 210 211 /* Step 2: Select GPIO for overcurrent indication, if desired. SKIP */ 212 213 /* Step 3: Assert all resets. */ 214 uctl_ctl = ioread64(uctl_ctl_reg); 215 uctl_ctl |= UCTL_CTL_UCTL_RST | UCTL_CTL_UAHC_RST | UCTL_CTL_UPHY_RST; 216 iowrite64(uctl_ctl, uctl_ctl_reg); 217 218 /* Step 4a: Reset the clock dividers. */ 219 uctl_ctl = ioread64(uctl_ctl_reg); 220 uctl_ctl |= UCTL_CTL_H_CLKDIV_RST; 221 iowrite64(uctl_ctl, uctl_ctl_reg); 222 223 /* Step 4b: Select controller clock frequency. */ 224 for (div = ARRAY_SIZE(clk_div) - 1; div >= 0; div--) { 225 h_clk_rate = gd->bus_clk / clk_div[div]; 226 if (h_clk_rate <= OCTEON_MAX_H_CLK_RATE && 227 h_clk_rate >= OCTEON_MIN_H_CLK_RATE) 228 break; 229 } 230 uctl_ctl = ioread64(uctl_ctl_reg); 231 uctl_ctl &= ~UCTL_CTL_H_CLKDIV_SEL; 232 uctl_ctl |= FIELD_PREP(UCTL_CTL_H_CLKDIV_SEL, div); 233 uctl_ctl |= UCTL_CTL_H_CLK_EN; 234 iowrite64(uctl_ctl, uctl_ctl_reg); 235 uctl_ctl = ioread64(uctl_ctl_reg); 236 if (div != FIELD_GET(UCTL_CTL_H_CLKDIV_SEL, uctl_ctl) || 237 !(uctl_ctl & UCTL_CTL_H_CLK_EN)) { 238 printf("dwc3 controller clock init failure\n"); 239 return -EINVAL; 240 } 241 242 /* Step 4c: Deassert the controller clock divider reset. */ 243 uctl_ctl = ioread64(uctl_ctl_reg); 244 uctl_ctl &= ~UCTL_CTL_H_CLKDIV_RST; 245 iowrite64(uctl_ctl, uctl_ctl_reg); 246 247 /* Step 5a: Reference clock configuration. */ 248 uctl_ctl = ioread64(uctl_ctl_reg); 249 uctl_ctl &= ~UCTL_CTL_REF_CLK_SEL; 250 uctl_ctl |= FIELD_PREP(UCTL_CTL_REF_CLK_SEL, ref_clk_sel); 251 uctl_ctl &= ~UCTL_CTL_REF_CLK_FSEL; 252 uctl_ctl |= FIELD_PREP(UCTL_CTL_REF_CLK_FSEL, 0x07); 253 uctl_ctl &= ~UCTL_CTL_REF_CLK_DIV2; 254 255 switch (clock_rate) { 256 default: 257 printf("Invalid ref_clk %u, using %u instead\n", CLOCK_100MHZ, 258 clock_rate); 259 fallthrough; 260 case CLOCK_100MHZ: 261 mpll_mul = 0x19; 262 if (ref_clk_sel < 2) { 263 uctl_ctl &= ~UCTL_CTL_REF_CLK_FSEL; 264 uctl_ctl |= FIELD_PREP(UCTL_CTL_REF_CLK_FSEL, 0x27); 265 } 266 break; 267 case CLOCK_50MHZ: 268 mpll_mul = 0x32; 269 break; 270 case CLOCK_125MHZ: 271 mpll_mul = 0x28; 272 break; 273 } 274 uctl_ctl &= ~UCTL_CTL_MPLL_MULTIPLIER; 275 uctl_ctl |= FIELD_PREP(UCTL_CTL_MPLL_MULTIPLIER, mpll_mul); 276 277 /* Step 5b: Configure and enable spread-spectrum for SuperSpeed. */ 278 uctl_ctl |= UCTL_CTL_SSC_EN; 279 280 /* Step 5c: Enable SuperSpeed. */ 281 uctl_ctl |= UCTL_CTL_REF_SSP_EN; 282 283 /* Step 5d: Configure PHYs. SKIP */ 284 285 /* Step 6a & 6b: Power up PHYs. */ 286 uctl_ctl |= UCTL_CTL_HS_POWER_EN; 287 uctl_ctl |= UCTL_CTL_SS_POWER_EN; 288 iowrite64(uctl_ctl, uctl_ctl_reg); 289 290 /* Step 7: Wait 10 controller-clock cycles to take effect. */ 291 udelay(10); 292 293 /* Step 8a: Deassert UCTL reset signal. */ 294 uctl_ctl = ioread64(uctl_ctl_reg); 295 uctl_ctl &= ~UCTL_CTL_UCTL_RST; 296 iowrite64(uctl_ctl, uctl_ctl_reg); 297 298 /* Step 8b: Wait 10 controller-clock cycles. */ 299 udelay(10); 300 301 /* Step 8c: Setup power-power control. */ 302 if (dwc3_octeon_config_power(dev, base)) { 303 printf("Error configuring power\n"); 304 return -EINVAL; 305 } 306 307 /* Step 8d: Deassert UAHC reset signal. */ 308 uctl_ctl = ioread64(uctl_ctl_reg); 309 uctl_ctl &= ~UCTL_CTL_UAHC_RST; 310 iowrite64(uctl_ctl, uctl_ctl_reg); 311 312 /* Step 8e: Wait 10 controller-clock cycles. */ 313 udelay(10); 314 315 /* Step 9: Enable conditional coprocessor clock of UCTL. */ 316 uctl_ctl = ioread64(uctl_ctl_reg); 317 uctl_ctl |= UCTL_CTL_SCLK_EN; 318 iowrite64(uctl_ctl, uctl_ctl_reg); 319 320 /* Step 10: Set for host mode only. */ 321 uctl_ctl = ioread64(uctl_ctl_reg); 322 uctl_ctl &= ~UCTL_CTL_DRD_MODE; 323 iowrite64(uctl_ctl, uctl_ctl_reg); 324 325 return 0; 326} 327 328static void dwc3_octeon_set_endian_mode(void __iomem *base) 329{ 330 u64 shim_cfg; 331 332 shim_cfg = ioread64(base + UCTL_SHIM_CFG); 333 shim_cfg &= ~UCTL_SHIM_CFG_CSR_ENDIAN_MODE; 334 shim_cfg |= FIELD_PREP(UCTL_SHIM_CFG_CSR_ENDIAN_MODE, 1); 335 shim_cfg &= ~UCTL_SHIM_CFG_DMA_ENDIAN_MODE; 336 shim_cfg |= FIELD_PREP(UCTL_SHIM_CFG_DMA_ENDIAN_MODE, 1); 337 iowrite64(shim_cfg, base + UCTL_SHIM_CFG); 338} 339 340static void dwc3_octeon_phy_reset(void __iomem *base) 341{ 342 u64 uctl_ctl; 343 344 uctl_ctl = ioread64(base); 345 uctl_ctl &= ~UCTL_CTL_UPHY_RST; 346 iowrite64(uctl_ctl, base); 347} 348 349static int octeon_dwc3_glue_probe(struct udevice *dev) 350{ 351 void __iomem *base; 352 353 base = dev_remap_addr(dev); 354 if (IS_ERR(base)) 355 return PTR_ERR(base); 356 357 dwc3_octeon_clocks_start(dev, base); 358 dwc3_octeon_set_endian_mode(base); 359 dwc3_octeon_phy_reset(base); 360 361 return 0; 362} 363 364static int octeon_dwc3_glue_bind(struct udevice *dev) 365{ 366 ofnode node, dwc3_node; 367 368 /* Find snps,dwc3 node from subnode */ 369 dwc3_node = ofnode_null(); 370 ofnode_for_each_subnode(node, dev_ofnode(dev)) { 371 if (ofnode_device_is_compatible(node, "snps,dwc3")) 372 dwc3_node = node; 373 } 374 375 if (!ofnode_valid(dwc3_node)) { 376 printf("Can't find dwc3 subnode for %s\n", dev->name); 377 return -ENODEV; 378 } 379 380 return dm_scan_fdt_dev(dev); 381} 382 383static const struct udevice_id octeon_dwc3_glue_ids[] = { 384 { .compatible = "cavium,octeon-7130-usb-uctl" }, 385 { } 386}; 387 388U_BOOT_DRIVER(dwc3_octeon_glue) = { 389 .name = "dwc3_octeon_glue", 390 .id = UCLASS_NOP, 391 .of_match = octeon_dwc3_glue_ids, 392 .probe = octeon_dwc3_glue_probe, 393 .bind = octeon_dwc3_glue_bind, 394 .flags = DM_FLAG_ALLOC_PRIV_DMA, 395}; 396