1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (c) 2012 The Chromium OS Authors.
4 *
5 * TSC calibration codes are adapted from Linux kernel
6 * arch/x86/kernel/tsc_msr.c and arch/x86/kernel/tsc.c
7 */
8
9#include <bootstage.h>
10#include <dm.h>
11#include <log.h>
12#include <malloc.h>
13#include <time.h>
14#include <timer.h>
15#include <asm/cpu.h>
16#include <asm/global_data.h>
17#include <asm/io.h>
18#include <asm/i8254.h>
19#include <asm/ibmpc.h>
20#include <asm/msr.h>
21#include <asm/u-boot-x86.h>
22#include <linux/delay.h>
23
24#define MAX_NUM_FREQS	9
25
26#define INTEL_FAM6_SKYLAKE_MOBILE	0x4E
27#define INTEL_FAM6_ATOM_GOLDMONT	0x5C /* Apollo Lake */
28#define INTEL_FAM6_SKYLAKE_DESKTOP	0x5E
29#define INTEL_FAM6_ATOM_GOLDMONT_X	0x5F /* Denverton */
30#define INTEL_FAM6_KABYLAKE_MOBILE	0x8E
31#define INTEL_FAM6_KABYLAKE_DESKTOP	0x9E
32
33DECLARE_GLOBAL_DATA_PTR;
34
35/*
36 * native_calibrate_tsc
37 * Determine TSC frequency via CPUID, else return 0.
38 */
39static unsigned long native_calibrate_tsc(void)
40{
41	struct cpuid_result tsc_info;
42	unsigned int crystal_freq;
43
44	if (gd->arch.x86_vendor != X86_VENDOR_INTEL)
45		return 0;
46
47	if (cpuid_eax(0) < 0x15)
48		return 0;
49
50	tsc_info = cpuid(0x15);
51
52	if (tsc_info.ebx == 0 || tsc_info.eax == 0)
53		return 0;
54
55	crystal_freq = tsc_info.ecx / 1000;
56	if (!CONFIG_IS_ENABLED(X86_TSC_TIMER_NATIVE) && !crystal_freq) {
57		switch (gd->arch.x86_model) {
58		case INTEL_FAM6_SKYLAKE_MOBILE:
59		case INTEL_FAM6_SKYLAKE_DESKTOP:
60		case INTEL_FAM6_KABYLAKE_MOBILE:
61		case INTEL_FAM6_KABYLAKE_DESKTOP:
62			crystal_freq = 24000;	/* 24.0 MHz */
63			break;
64		case INTEL_FAM6_ATOM_GOLDMONT_X:
65			crystal_freq = 25000;	/* 25.0 MHz */
66			break;
67		case INTEL_FAM6_ATOM_GOLDMONT:
68			crystal_freq = 19200;	/* 19.2 MHz */
69			break;
70		default:
71			return 0;
72		}
73	}
74
75	return (crystal_freq * tsc_info.ebx / tsc_info.eax) / 1000;
76}
77
78static unsigned long cpu_mhz_from_cpuid(void)
79{
80	if (gd->arch.x86_vendor != X86_VENDOR_INTEL)
81		return 0;
82
83	if (cpuid_eax(0) < 0x16)
84		return 0;
85
86	return cpuid_eax(0x16);
87}
88
89/*
90 * According to Intel 64 and IA-32 System Programming Guide,
91 * if MSR_PERF_STAT[31] is set, the maximum resolved bus ratio can be
92 * read in MSR_PLATFORM_ID[12:8], otherwise in MSR_PERF_STAT[44:40].
93 * Unfortunately some Intel Atom SoCs aren't quite compliant to this,
94 * so we need manually differentiate SoC families. This is what the
95 * field msr_plat does.
96 */
97struct freq_desc {
98	u8 x86_family;	/* CPU family */
99	u8 x86_model;	/* model */
100	/* 2: use 100MHz, 1: use MSR_PLATFORM_INFO, 0: MSR_IA32_PERF_STATUS */
101	u8 msr_plat;
102	u32 freqs[MAX_NUM_FREQS];
103};
104
105static struct freq_desc freq_desc_tables[] = {
106	/* PNW */
107	{ 6, 0x27, 0, { 0, 0, 0, 0, 0, 99840, 0, 83200, 0 } },
108	/* CLV+ */
109	{ 6, 0x35, 0, { 0, 133200, 0, 0, 0, 99840, 0, 83200, 0 } },
110	/* TNG - Intel Atom processor Z3400 series */
111	{ 6, 0x4a, 1, { 0, 100000, 133300, 0, 0, 0, 0, 0, 0 } },
112	/* VLV2 - Intel Atom processor E3000, Z3600, Z3700 series */
113	{ 6, 0x37, 1, { 83300, 100000, 133300, 116700, 80000, 0, 0, 0, 0 } },
114	/* ANN - Intel Atom processor Z3500 series */
115	{ 6, 0x5a, 1, { 83300, 100000, 133300, 100000, 0, 0, 0, 0, 0 } },
116	/* AMT - Intel Atom processor X7-Z8000 and X5-Z8000 series */
117	{ 6, 0x4c, 1, { 83300, 100000, 133300, 116700,
118			80000, 93300, 90000, 88900, 87500 } },
119	/* Ivybridge */
120	{ 6, 0x3a, 2, { 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
121};
122
123static int match_cpu(u8 family, u8 model)
124{
125	int i;
126
127	for (i = 0; i < ARRAY_SIZE(freq_desc_tables); i++) {
128		if ((family == freq_desc_tables[i].x86_family) &&
129		    (model == freq_desc_tables[i].x86_model))
130			return i;
131	}
132
133	return -1;
134}
135
136/* Map CPU reference clock freq ID(0-7) to CPU reference clock freq(KHz) */
137#define id_to_freq(cpu_index, freq_id) \
138	(freq_desc_tables[cpu_index].freqs[freq_id])
139
140/*
141 * TSC on Intel Atom SoCs capable of determining TSC frequency by MSR is
142 * reliable and the frequency is known (provided by HW).
143 *
144 * On these platforms PIT/HPET is generally not available so calibration won't
145 * work at all and there is no other clocksource to act as a watchdog for the
146 * TSC, so we have no other choice than to trust it.
147 *
148 * Returns the TSC frequency in MHz or 0 if HW does not provide it.
149 */
150static unsigned long __maybe_unused cpu_mhz_from_msr(void)
151{
152	u32 lo, hi, ratio, freq_id, freq;
153	unsigned long res;
154	int cpu_index;
155
156	if (gd->arch.x86_vendor != X86_VENDOR_INTEL)
157		return 0;
158
159	cpu_index = match_cpu(gd->arch.x86, gd->arch.x86_model);
160	if (cpu_index < 0)
161		return 0;
162
163	if (freq_desc_tables[cpu_index].msr_plat) {
164		rdmsr(MSR_PLATFORM_INFO, lo, hi);
165		ratio = (lo >> 8) & 0xff;
166	} else {
167		rdmsr(MSR_IA32_PERF_STATUS, lo, hi);
168		ratio = (hi >> 8) & 0x1f;
169	}
170	debug("Maximum core-clock to bus-clock ratio: 0x%x\n", ratio);
171
172	if (freq_desc_tables[cpu_index].msr_plat == 2) {
173		/* TODO: Figure out how best to deal with this */
174		freq = 100000;
175		debug("Using frequency: %u KHz\n", freq);
176	} else {
177		/* Get FSB FREQ ID */
178		rdmsr(MSR_FSB_FREQ, lo, hi);
179		freq_id = lo & 0x7;
180		freq = id_to_freq(cpu_index, freq_id);
181		debug("Resolved frequency ID: %u, frequency: %u KHz\n",
182		      freq_id, freq);
183	}
184
185	/* TSC frequency = maximum resolved freq * maximum resolved bus ratio */
186	res = freq * ratio / 1000;
187	debug("TSC runs at %lu MHz\n", res);
188
189	return res;
190}
191
192/*
193 * This reads the current MSB of the PIT counter, and
194 * checks if we are running on sufficiently fast and
195 * non-virtualized hardware.
196 *
197 * Our expectations are:
198 *
199 *  - the PIT is running at roughly 1.19MHz
200 *
201 *  - each IO is going to take about 1us on real hardware,
202 *    but we allow it to be much faster (by a factor of 10) or
203 *    _slightly_ slower (ie we allow up to a 2us read+counter
204 *    update - anything else implies a unacceptably slow CPU
205 *    or PIT for the fast calibration to work.
206 *
207 *  - with 256 PIT ticks to read the value, we have 214us to
208 *    see the same MSB (and overhead like doing a single TSC
209 *    read per MSB value etc).
210 *
211 *  - We're doing 2 reads per loop (LSB, MSB), and we expect
212 *    them each to take about a microsecond on real hardware.
213 *    So we expect a count value of around 100. But we'll be
214 *    generous, and accept anything over 50.
215 *
216 *  - if the PIT is stuck, and we see *many* more reads, we
217 *    return early (and the next caller of pit_expect_msb()
218 *    then consider it a failure when they don't see the
219 *    next expected value).
220 *
221 * These expectations mean that we know that we have seen the
222 * transition from one expected value to another with a fairly
223 * high accuracy, and we didn't miss any events. We can thus
224 * use the TSC value at the transitions to calculate a pretty
225 * good value for the TSC frequencty.
226 */
227static inline int pit_verify_msb(unsigned char val)
228{
229	/* Ignore LSB */
230	inb(0x42);
231	return inb(0x42) == val;
232}
233
234static inline int pit_expect_msb(unsigned char val, u64 *tscp,
235				 unsigned long *deltap)
236{
237	int count;
238	u64 tsc = 0, prev_tsc = 0;
239
240	for (count = 0; count < 50000; count++) {
241		if (!pit_verify_msb(val))
242			break;
243		prev_tsc = tsc;
244		tsc = rdtsc();
245	}
246	*deltap = rdtsc() - prev_tsc;
247	*tscp = tsc;
248
249	/*
250	 * We require _some_ success, but the quality control
251	 * will be based on the error terms on the TSC values.
252	 */
253	return count > 5;
254}
255
256/*
257 * How many MSB values do we want to see? We aim for
258 * a maximum error rate of 500ppm (in practice the
259 * real error is much smaller), but refuse to spend
260 * more than 50ms on it.
261 */
262#define MAX_QUICK_PIT_MS 50
263#define MAX_QUICK_PIT_ITERATIONS (MAX_QUICK_PIT_MS * PIT_TICK_RATE / 1000 / 256)
264
265static unsigned long __maybe_unused quick_pit_calibrate(void)
266{
267	int i;
268	u64 tsc, delta;
269	unsigned long d1, d2;
270
271	/* Set the Gate high, disable speaker */
272	outb((inb(0x61) & ~0x02) | 0x01, 0x61);
273
274	/*
275	 * Counter 2, mode 0 (one-shot), binary count
276	 *
277	 * NOTE! Mode 2 decrements by two (and then the
278	 * output is flipped each time, giving the same
279	 * final output frequency as a decrement-by-one),
280	 * so mode 0 is much better when looking at the
281	 * individual counts.
282	 */
283	outb(0xb0, 0x43);
284
285	/* Start at 0xffff */
286	outb(0xff, 0x42);
287	outb(0xff, 0x42);
288
289	/*
290	 * The PIT starts counting at the next edge, so we
291	 * need to delay for a microsecond. The easiest way
292	 * to do that is to just read back the 16-bit counter
293	 * once from the PIT.
294	 */
295	pit_verify_msb(0);
296
297	if (pit_expect_msb(0xff, &tsc, &d1)) {
298		for (i = 1; i <= MAX_QUICK_PIT_ITERATIONS; i++) {
299			if (!pit_expect_msb(0xff-i, &delta, &d2))
300				break;
301
302			/*
303			 * Iterate until the error is less than 500 ppm
304			 */
305			delta -= tsc;
306			if (d1+d2 >= delta >> 11)
307				continue;
308
309			/*
310			 * Check the PIT one more time to verify that
311			 * all TSC reads were stable wrt the PIT.
312			 *
313			 * This also guarantees serialization of the
314			 * last cycle read ('d2') in pit_expect_msb.
315			 */
316			if (!pit_verify_msb(0xfe - i))
317				break;
318			goto success;
319		}
320	}
321	debug("Fast TSC calibration failed\n");
322	return 0;
323
324success:
325	/*
326	 * Ok, if we get here, then we've seen the
327	 * MSB of the PIT decrement 'i' times, and the
328	 * error has shrunk to less than 500 ppm.
329	 *
330	 * As a result, we can depend on there not being
331	 * any odd delays anywhere, and the TSC reads are
332	 * reliable (within the error).
333	 *
334	 * kHz = ticks / time-in-seconds / 1000;
335	 * kHz = (t2 - t1) / (I * 256 / PIT_TICK_RATE) / 1000
336	 * kHz = ((t2 - t1) * PIT_TICK_RATE) / (I * 256 * 1000)
337	 */
338	delta *= PIT_TICK_RATE;
339	delta /= (i*256*1000);
340	debug("Fast TSC calibration using PIT\n");
341	return delta / 1000;
342}
343
344/* Get the speed of the TSC timer in MHz */
345unsigned notrace long get_tbclk_mhz(void)
346{
347	return get_tbclk() / 1000000;
348}
349
350static ulong get_ms_timer(void)
351{
352	return (get_ticks() * 1000) / get_tbclk();
353}
354
355ulong get_timer(ulong base)
356{
357	return get_ms_timer() - base;
358}
359
360ulong notrace timer_get_us(void)
361{
362	return get_ticks() / get_tbclk_mhz();
363}
364
365ulong timer_get_boot_us(void)
366{
367	return timer_get_us();
368}
369
370void __udelay(unsigned long usec)
371{
372	u64 now = get_ticks();
373	u64 stop;
374
375	stop = now + (u64)usec * get_tbclk_mhz();
376
377	while ((int64_t)(stop - get_ticks()) > 0)
378#if defined(CONFIG_QEMU) && defined(CONFIG_SMP)
379		/*
380		 * Add a 'pause' instruction on qemu target,
381		 * to give other VCPUs a chance to run.
382		 */
383		asm volatile("pause");
384#else
385		;
386#endif
387}
388
389static u64 tsc_timer_get_count(struct udevice *dev)
390{
391	u64 now_tick = rdtsc();
392
393	return now_tick - gd->arch.tsc_base;
394}
395
396static void tsc_timer_ensure_setup(bool early)
397{
398	if (gd->arch.tsc_inited)
399		return;
400	if (IS_ENABLED(CONFIG_X86_TSC_READ_BASE))
401		gd->arch.tsc_base = rdtsc();
402
403	if (!gd->arch.clock_rate) {
404		unsigned long fast_calibrate;
405
406		/**
407		 * There is no obvious way to obtain this information from EFI
408		 * boot services. This value was measured on a Framework Laptop
409		 * which has a 12th Gen Intel Core
410		 */
411		if (IS_ENABLED(CONFIG_EFI_APP)) {
412			fast_calibrate = 2750;
413			goto done;
414		}
415		fast_calibrate = native_calibrate_tsc();
416		if (fast_calibrate)
417			goto done;
418
419		/* Reduce code size by dropping other methods */
420		if (CONFIG_IS_ENABLED(X86_TSC_TIMER_NATIVE))
421			panic("no timer");
422
423		fast_calibrate = cpu_mhz_from_cpuid();
424		if (fast_calibrate)
425			goto done;
426
427		fast_calibrate = cpu_mhz_from_msr();
428		if (fast_calibrate)
429			goto done;
430
431		fast_calibrate = quick_pit_calibrate();
432		if (fast_calibrate)
433			goto done;
434
435		if (early)
436			gd->arch.clock_rate = CONFIG_X86_TSC_TIMER_FREQ;
437		else
438			return;
439
440done:
441		if (!gd->arch.clock_rate)
442			gd->arch.clock_rate = fast_calibrate * 1000000;
443	}
444	gd->arch.tsc_inited = true;
445}
446
447static int tsc_timer_probe(struct udevice *dev)
448{
449	struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
450
451	/* Try hardware calibration first */
452	tsc_timer_ensure_setup(false);
453	if (!gd->arch.clock_rate) {
454		/*
455		 * Use the clock frequency specified in the
456		 * device tree as last resort
457		 */
458		if (!uc_priv->clock_rate)
459			panic("TSC frequency is ZERO");
460	} else {
461		uc_priv->clock_rate = gd->arch.clock_rate;
462	}
463
464	return 0;
465}
466
467unsigned long notrace timer_early_get_rate(void)
468{
469	/*
470	 * When TSC timer is used as the early timer, be warned that the timer
471	 * clock rate can only be calibrated via some hardware ways. Specifying
472	 * it in the device tree won't work for the early timer.
473	 */
474	tsc_timer_ensure_setup(true);
475
476	return gd->arch.clock_rate;
477}
478
479u64 notrace timer_early_get_count(void)
480{
481	tsc_timer_ensure_setup(true);
482
483	return rdtsc() - gd->arch.tsc_base;
484}
485
486static const struct timer_ops tsc_timer_ops = {
487	.get_count = tsc_timer_get_count,
488};
489
490#if CONFIG_IS_ENABLED(OF_REAL)
491static const struct udevice_id tsc_timer_ids[] = {
492	{ .compatible = "x86,tsc-timer", },
493	{ }
494};
495#endif
496
497U_BOOT_DRIVER(x86_tsc_timer) = {
498	.name	= "x86_tsc_timer",
499	.id	= UCLASS_TIMER,
500	.of_match = of_match_ptr(tsc_timer_ids),
501	.probe = tsc_timer_probe,
502	.ops	= &tsc_timer_ops,
503};
504