Searched refs:ccr (Results 1 - 25 of 46) sorted by relevance

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/u-boot/arch/sh/cpu/sh4/
H A Dcache.c41 unsigned long ccr; local
44 ccr = inl(CCR);
46 if (ccr & CCR_CACHE_ENABLE)
/u-boot/arch/arm/include/asm/arch-sunxi/
H A Drsb.h18 u32 ccr; /* 0x04 */ member in struct:sunxi_rsb_reg
H A Ddram_sun8i_a23.h46 u32 ccr; /* 0x04 controller configuration register */ member in struct:sunxi_mctl_com_reg
/u-boot/drivers/spi/
H A Dstm32_qspi.c34 u32 ccr; /* 0x14 */ member in struct:stm32_qspi_regs
243 u32 cr, ccr, addr_max; local
264 ccr = (mode << STM32_QSPI_CCR_FMODE_SHIFT);
265 ccr |= op->cmd.opcode;
266 ccr |= (_stm32_qspi_get_mode(op->cmd.buswidth)
270 ccr |= ((op->addr.nbytes - 1) << STM32_QSPI_CCR_ADSIZE_SHIFT);
271 ccr |= (_stm32_qspi_get_mode(op->addr.buswidth)
276 ccr |= (op->dummy.nbytes * 8 / op->dummy.buswidth
280 ccr |= (_stm32_qspi_get_mode(op->data.buswidth)
283 writel(ccr,
[all...]
/u-boot/arch/arm/mach-at91/arm920t/
H A Dtimer.c42 writel(AT91_TC_CCR_CLKDIS, &tc->tc[0].ccr);
50 writel(AT91_TC_CCR_SWTRG | AT91_TC_CCR_CLKEN, &tc->tc[0].ccr);
/u-boot/arch/arm/cpu/armv7m/
H A Dcache.c214 setbits_le32(&V7M_SCB->ccr, BIT(V7M_CCR_DCACHE));
232 clrbits_le32(&V7M_SCB->ccr, BIT(V7M_CCR_DCACHE));
241 return (readl(&V7M_SCB->ccr) & BIT(V7M_CCR_DCACHE)) != 0;
322 setbits_le32(&V7M_SCB->ccr, BIT(V7M_CCR_ICACHE));
331 return (readl(&V7M_SCB->ccr) & BIT(V7M_CCR_ICACHE)) != 0;
340 clrbits_le32(&V7M_SCB->ccr, BIT(V7M_CCR_ICACHE));
/u-boot/arch/powerpc/lib/
H A Dkgdb.c174 *ptr++ = regs->ccr;
207 case 66: regs->ccr = *ptr; break;
244 regs->ccr = *ptr++;
/u-boot/drivers/watchdog/
H A Dcdns_wdt.c21 u32 ccr; /* Counter Control Register offset - 0x4 */ member in struct:cdns_regs
177 cdns_wdt_writereg(&priv->regs->ccr, data);
245 cdns_wdt_writereg(&priv->regs->ccr, data);
/u-boot/board/ronetix/pm9g45/
H A Dpm9g45.c45 csa = readl(&matrix->ccr[6]) | AT91_MATRIX_CSA_EBI_CS3A;
46 writel(csa, &matrix->ccr[6]);
/u-boot/arch/arm/mach-sunxi/
H A Ddram_sun4i.c116 clrsetbits_le32(&dram->ccr, DRAM_CCR_INIT, DRAM_CCR_ITM_OFF);
123 clrbits_le32(&dram->ccr, DRAM_CCR_ITM_OFF);
392 setbits_le32(&dram->ccr, DRAM_CCR_DATA_TRAINING);
395 await_bits_clear(&dram->ccr, DRAM_CCR_DATA_TRAINING);
504 setbits_le32(&dram->ccr, DRAM_CCR_INIT);
505 await_bits_clear(&dram->ccr, DRAM_CCR_INIT);
631 await_bits_clear(&dram->ccr, DRAM_CCR_INIT);
656 clrsetbits_le32(&dram->ccr, DRAM_CCR_DQS_DRIFT_COMP, DRAM_CCR_DQS_GATE);
661 setbits_le32(&dram->ccr, DRAM_CCR_COMMAND_RATE_1T);
681 clrbits_le32(&dram->ccr, DRAM_CCR_DQS_GAT
[all...]
H A Ddram_sun6i.c177 clrbits_le32(&mctl_com->ccr, MCTL_CCR_CH1_CLK_EN);
352 setbits_le32(&mctl_com->ccr, MCTL_CCR_CH0_CLK_EN);
356 setbits_le32(&mctl_com->ccr, MCTL_CCR_CH1_CLK_EN);
359 setbits_le32(&mctl_com->ccr, MCTL_CCR_MASTER_CLK_EN);
H A Ddram_sun9i.c301 setbits_le32(&mctl_com->ccr, (1 << 14) | (1 << 30));
331 clrbits_le32(&mctl_com->ccr, MCTL_CCR_CH0_CLK_EN | MCTL_CCR_CH1_CLK_EN);
334 setbits_le32(&mctl_com->ccr, MCTL_CCR_CH0_CLK_EN);
336 setbits_le32(&mctl_com->ccr, MCTL_CCR_CH1_CLK_EN);
/u-boot/arch/powerpc/include/asm/
H A Dptrace.h34 PPC_REG ccr; member in struct:pt_regs
/u-boot/arch/arm/include/asm/arch-lpc32xx/
H A Dtimer.h20 u32 ccr; /* Capture Control Register */ member in struct:timer_regs
/u-boot/arch/arm/include/asm/
H A Darmv7m.h32 uint32_t ccr; /* offset 0x14: Config and Control Register */ member in struct:v7m_scb
/u-boot/arch/arm/mach-at91/include/mach/
H A Dat91_tc.h10 u32 ccr; /* 0x00 Channel Control Register */ member in struct:at91_tcc
H A Dat91_matrix.h66 u32 ccr[52]; /* 0x110 - 0x1E0 Chip Configuration */ member in struct:at91_matrix
/u-boot/arch/m68k/cpu/mcf5445x/
H A Dspeed.c72 bootmod_ccr = (in_be16(&ccm->ccr) & CCM_CCR_BOOTMOD) >> 14;
/u-boot/drivers/mmc/
H A Dftsdc010_mci.c146 writel(FTSDC010_CCR_CLK_DIV(div), &regs->ccr);
149 setbits_le32(&regs->ccr, FTSDC010_CCR_CLK_SD);
152 setbits_le32(&regs->ccr, FTSDC010_CCR_CLK_HISPD);
154 clrbits_le32(&regs->ccr, FTSDC010_CCR_CLK_HISPD);
/u-boot/board/dhelectronics/dh_stm32mp1/
H A Dboard.c80 u32 reg, cider, ccr; local
105 ccr = readw(reg);
106 if (ccr & KS_CCR_EEPROM)
/u-boot/arch/m68k/include/asm/coldfire/
H A Dssi.h22 u32 ccr; member in struct:ssi
/u-boot/include/faraday/
H A Dftsdc010.h31 unsigned int ccr; /* 0x38 - clock contorl reg */ member in struct:ftsdc010_mmc
/u-boot/arch/arm/lib/
H A Dasm-offsets.c44 DEFINE(CLKCTL_CCMR, offsetof(struct clkctl, ccr));
/u-boot/arch/arm/mach-imx/mx5/
H A Dclock.c220 u32 ccr = readl(&mxc_ccm->ccr); local
222 if (ccr & MXC_CCM_CCR_FPM_MULT)
/u-boot/arch/arm/include/asm/arch-vf610/
H A Dcrm_regs.h15 u32 ccr; member in struct:ccm_reg

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