1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com>
4 */
5
6#ifndef _LPC32XX_TIMER_H
7#define _LPC32XX_TIMER_H
8
9#include <asm/types.h>
10
11/* Timer/Counter Registers */
12struct timer_regs {
13	u32 ir;			/* Interrupt Register		*/
14	u32 tcr;		/* Timer Control Register	*/
15	u32 tc;			/* Timer Counter		*/
16	u32 pr;			/* Prescale Register		*/
17	u32 pc;			/* Prescale Counter		*/
18	u32 mcr;		/* Match Control Register	*/
19	u32 mr[4];		/* Match Registers		*/
20	u32 ccr;		/* Capture Control Register	*/
21	u32 cr[4];		/* Capture Registers		*/
22	u32 emr;		/* External Match Register	*/
23	u32 reserved[12];
24	u32 ctcr;		/* Count Control Register	*/
25};
26
27/* Timer/Counter Interrupt Register bits */
28#define TIMER_IR_CR(n)			(1 << ((n) + 4))
29#define TIMER_IR_MR(n)			(1 << (n))
30
31/* Timer/Counter Timer Control Register bits */
32#define TIMER_TCR_COUNTER_RESET		(1 << 1)
33#define TIMER_TCR_COUNTER_ENABLE	(1 << 0)
34#define TIMER_TCR_COUNTER_DISABLE	(0 << 0)
35
36/* Timer/Counter Match Control Register bits */
37#define TIMER_MCR_STOP(n)		(1 << (3 * (n) + 2))
38#define TIMER_MCR_RESET(n)		(1 << (3 * (n) + 1))
39#define TIMER_MCR_INTERRUPT(n)		(1 << (3 * (n)))
40
41/* Timer/Counter Capture Control Register bits */
42#define TIMER_CCR_INTERRUPT(n)		(1 << (3 * (n) + 2))
43#define TIMER_CCR_FALLING_EDGE(n)	(1 << (3 * (n) + 1))
44#define TIMER_CCR_RISING_EDGE(n)	(1 << (3 * (n)))
45
46/* Timer/Counter External Match Register bits */
47#define TIMER_EMR_EMC_TOGGLE(n)		(0x3 << (2 * (n) + 4))
48#define TIMER_EMR_EMC_SET(n)		(0x2 << (2 * (n) + 4))
49#define TIMER_EMR_EMC_CLEAR(n)		(0x1 << (2 * (n) + 4))
50#define TIMER_EMR_EMC_NOTHING(n)	(0x0 << (2 * (n) + 4))
51#define TIMER_EMR_EM(n)			(1 << (n))
52
53/* Timer/Counter Count Control Register bits */
54#define TIMER_CTCR_INPUT(n)		((n) << 2)
55#define TIMER_CTCR_MODE_COUNTER_BOTH	(0x3 << 0)
56#define TIMER_CTCR_MODE_COUNTER_FALLING	(0x2 << 0)
57#define TIMER_CTCR_MODE_COUNTER_RISING	(0x1 << 0)
58#define TIMER_CTCR_MODE_TIMER		(0x0 << 0)
59
60#endif /* _LPC32XX_TIMER_H */
61