/u-boot/drivers/clk/renesas/ |
H A D | rzg2l-cpg.h | 137 #define DEF_TYPE(_name, _id, _type...) \ 138 { .name = _name, .id = _id, .type = _type } 139 #define DEF_BASE(_name, _id, _type, _parent...) \ 140 DEF_TYPE(_name, _id, _type, .parent = _parent) 141 #define DEF_SAMPLL(_name, _id, _parent, _conf) \ 142 DEF_TYPE(_name, _id, CLK_TYPE_SAM_PLL, .parent = _parent, .conf = _conf) 143 #define DEF_INPUT(_name, _id) \ 144 DEF_TYPE(_name, _id, CLK_TYPE_IN) 145 #define DEF_FIXED(_name, _id, _parent, _mult, _div) \ 146 DEF_BASE(_name, _id, CLK_TYPE_F [all...] |
H A D | rcar-gen3-cpg.h | 59 #define DEF_GEN3_SDH(_name, _id, _parent, _offset) \ 60 DEF_BASE(_name, _id, CLK_TYPE_GEN3_SDH, _parent, .offset = _offset) 62 #define DEF_GEN3_SD(_name, _id, _parent, _offset) \ 63 DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset) 65 #define DEF_GEN3_MDSEL(_name, _id, _md, _parent0, _div0, _parent1, _div1) \ 66 DEF_BASE(_name, _id, CLK_TYPE_GEN3_MDSEL, \ 70 #define DEF_GEN3_PE(_name, _id, _parent_sscg, _div_sscg, _parent_clean, \ 72 DEF_GEN3_MDSEL(_name, _id, 12, _parent_sscg, _div_sscg, \ 75 #define DEF_GEN3_OSC(_name, _id, _parent, _div) \ 76 DEF_BASE(_name, _id, CLK_TYPE_GEN3_OS [all...] |
H A D | renesas-cpg-mssr.h | 79 #define DEF_TYPE(_name, _id, _type...) \ 80 { .name = _name, .id = _id, .type = _type } 81 #define DEF_BASE(_name, _id, _type, _parent...) \ 82 DEF_TYPE(_name, _id, _type, .parent = _parent) 84 #define DEF_INPUT(_name, _id) \ 85 DEF_TYPE(_name, _id, CLK_TYPE_IN) 86 #define DEF_FIXED(_name, _id, _parent, _div, _mult) \ 87 DEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div = _div, .mult = _mult) 88 #define DEF_DIV6P1(_name, _id, _parent, _offset) \ 89 DEF_BASE(_name, _id, CLK_TYPE_DIV6P [all...] |
/u-boot/drivers/clk/exynos/ |
H A D | clk.h | 54 * @_id: local clock index (unique across @_cmu) 59 #define SAMSUNG_TO_CLK_ID(_cmu, _id) (((_cmu) << 8) | ((_id) & 0xff)) 87 #define __MUX(_id, cname, pnames, o, s, w, f, mf) \ 89 .id = _id, \ 100 #define MUX(_id, cname, pnames, o, s, w) \ 101 __MUX(_id, cname, pnames, o, s, w, 0, 0) 103 #define MUX_F(_id, cname, pnames, o, s, w, f, mf) \ 104 __MUX(_id, cname, pnames, o, s, w, f, mf) 128 #define __DIV(_id, cnam [all...] |
/u-boot/include/ |
H A D | k3-dev.h | 73 #define PSC(_id, _base) { .id = _id, .base = (void *)_base, } 74 #define PSC_PD(_id, _psc, _depend) { .id = _id, .psc = _psc, .depend = _depend } 75 #define PSC_LPSC(_id, _psc, _pd, _depend) { .id = _id, .psc = _psc, .pd = _pd, .depend = _depend } 76 #define PSC_DEV(_id, _lpsc) { .id = _id, .lpsc = _lpsc }
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/u-boot/drivers/clk/uniphier/ |
H A D | clk-uniphier.h | 50 #define UNIPHIER_CLK_RATE(_id, _rate) \ 53 .id = (_id), \ 59 #define UNIPHIER_CLK_GATE(_id, _parent, _reg, _bit) \ 62 .id = (_id), \ 70 #define UNIPHIER_CLK_GATE_SIMPLE(_id, _reg, _bit) \ 71 UNIPHIER_CLK_GATE(_id, UNIPHIER_CLK_ID_INVALID, _reg, _bit)
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H A D | clk-uniphier-mio.c | 19 #define UNIPHIER_MIO_CLK_SD(_id, ch) \ 22 .id = (_id) + 32, \ 58 UNIPHIER_CLK_GATE((_id), (_id) + 32, 0x20 + 0x200 * (ch), 8)
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H A D | clk-uniphier-sys.c | 9 #define UNIPHIER_LD4_SYS_CLK_NAND(_id) \ 11 UNIPHIER_CLK_GATE((_id), 128, 0x2104, 2) 13 #define UNIPHIER_LD11_SYS_CLK_NAND(_id) \ 15 UNIPHIER_CLK_GATE((_id), 128, 0x210c, 0)
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/u-boot/drivers/clk/mediatek/ |
H A D | clk-mtk.h | 69 #define FIXED_CLK(_id, _parent, _rate) { \ 70 .id = _id, \ 92 #define FACTOR(_id, _parent, _mult, _div, _flags) { \ 93 .id = _id, \ 129 #define MUX_GATE_FLAGS(_id, _parents, _reg, _shift, _width, _gate, \ 131 .id = _id, \ 142 #define MUX_GATE(_id, _parents, _reg, _shift, _width, _gate) \ 143 MUX_GATE_FLAGS(_id, _parents, _reg, _shift, _width, _gate, 0) 145 #define MUX(_id, _parents, _reg, _shift, _width) { \ 146 .id = _id, \ [all...] |
H A D | clk-mt7629.c | 33 #define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ 35 .id = _id, \ 65 #define FACTOR0(_id, _parent, _mult, _div) \ 66 FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED) 68 #define FACTOR1(_id, _parent, _mult, _div) \ 69 FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN) 71 #define FACTOR2(_id, _parent, _mult, _div) \ 72 FACTOR(_id, _parent, _mult, _div, 0) 427 #define GATE_INFRA(_id, _parent, _shift) { \ 428 .id = _id, \ [all...] |
H A D | clk-mt8365.c | 22 #define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ 24 .id = _id, \ 75 #define PLL_FACTOR(_id, _name, _parent, _mult, _div) \ 76 FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED) 510 #define GATE_TOP0(_id, _parent, _shift) { \ 511 .id = _id, \ 518 #define GATE_TOP1(_id, _parent, _shift) { \ 519 .id = _id, \ 526 #define GATE_TOP2(_id, _parent, _shift) { \ 527 .id = _id, \ [all...] |
H A D | clk-mt7622.c | 33 #define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ 35 .id = _id, \ 71 #define FACTOR0(_id, _parent, _mult, _div) \ 72 FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED) 74 #define FACTOR1(_id, _parent, _mult, _div) \ 75 FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN) 77 #define FACTOR2(_id, _parent, _mult, _div) \ 78 FACTOR(_id, _parent, _mult, _div, 0) 376 #define GATE_INFRA(_id, _parent, _shift) { \ 377 .id = _id, \ [all...] |
H A D | clk-mt8516.c | 21 #define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ 23 .id = _id, \ 53 #define FACTOR0(_id, _parent, _mult, _div) \ 54 FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED) 56 #define FACTOR1(_id, _parent, _mult, _div) \ 57 FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN) 59 #define FACTOR2(_id, _parent, _mult, _div) \ 60 FACTOR(_id, _parent, _mult, _div, 0) 578 #define GATE_TOP0(_id, _parent, _shift) { \ 579 .id = _id, \ [all...] |
H A D | clk-mt7986.c | 21 #define PLL_FACTOR(_id, _name, _parent, _mult, _div) \ 22 FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED) 24 #define TOP_FACTOR(_id, _name, _parent, _mult, _div) \ 25 FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN) 27 #define INFRA_FACTOR(_id, _name, _parent, _mult, _div) \ 28 FACTOR(_id, _parent, _mult, _div, CLK_PARENT_INFRASYS) 204 #define TOP_MUX(_id, _name, _parents, _mux_ofs, _mux_set_ofs, _mux_clr_ofs, \ 207 .id = _id, .mux_reg = _mux_ofs, .mux_set_reg = _mux_set_ofs, \ 373 #define INFRA_MUX(_id, _name, _parents, _reg, _shift, _width) \ 375 .id = _id, [all...] |
H A D | clk-mt8512.c | 22 #define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ 24 .id = _id, \ 63 #define FACTOR0(_id, _parent, _mult, _div) \ 64 FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED) 66 #define FACTOR1(_id, _parent, _mult, _div) \ 67 FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN) 69 #define FACTOR2(_id, _parent, _mult, _div) \ 70 FACTOR(_id, _parent, _mult, _div, 0) 611 #define GATE_TOP0(_id, _parent, _shift) { \ 612 .id = _id, \ [all...] |
H A D | clk-mt7988.c | 24 #define XTAL_FACTOR(_id, _name, _parent, _mult, _div) \ 25 FACTOR(_id, _parent, _mult, _div, CLK_PARENT_XTAL) 27 #define PLL_FACTOR(_id, _name, _parent, _mult, _div) \ 28 FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED) 30 #define TOP_FACTOR(_id, _name, _parent, _mult, _div) \ 31 FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN) 33 #define INFRA_FACTOR(_id, _name, _parent, _mult, _div) \ 34 FACTOR(_id, _parent, _mult, _div, CLK_PARENT_INFRASYS) 258 #define TOP_MUX(_id, _name, _parents, _mux_ofs, _mux_set_ofs, _mux_clr_ofs, \ 261 .id = _id, [all...] |
H A D | clk-mt8518.c | 21 #define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ 23 .id = _id, \ 55 #define FACTOR0(_id, _parent, _mult, _div) \ 56 FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED) 58 #define FACTOR1(_id, _parent, _mult, _div) \ 59 FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN) 61 #define FACTOR2(_id, _parent, _mult, _div) \ 62 FACTOR(_id, _parent, _mult, _div, 0) 1301 #define GATE_TOP0(_id, _parent, _shift) { \ 1302 .id = _id, \ [all...] |
H A D | clk-mt7623.c | 29 #define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ 31 .id = _id, \ 75 #define FACTOR0(_id, _parent, _mult, _div) \ 76 FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED) 78 #define FACTOR1(_id, _parent, _mult, _div) \ 79 FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN) 81 #define FACTOR2(_id, _parent, _mult, _div) \ 82 FACTOR(_id, _parent, _mult, _div, 0) 590 #define GATE_INFRA(_id, _parent, _shift) { \ 591 .id = _id, \ [all...] |
H A D | clk-mt7981.c | 21 #define PLL_FACTOR(_id, _name, _parent, _mult, _div) \ 22 FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED) 24 #define TOP_FACTOR(_id, _name, _parent, _mult, _div) \ 25 FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN) 27 #define INFRA_FACTOR(_id, _name, _parent, _mult, _div) \ 28 FACTOR(_id, _parent, _mult, _div, CLK_PARENT_INFRASYS) 231 #define TOP_MUX(_id, _name, _parents, _mux_ofs, _mux_set_ofs, _mux_clr_ofs, \ 234 .id = _id, .mux_reg = _mux_ofs, .mux_set_reg = _mux_set_ofs, \ 383 #define INFRA_MUX(_id, _name, _parents, _reg, _shift, _width) \ 385 .id = _id, [all...] |
/u-boot/arch/arm/include/asm/ |
H A D | secure.h | 22 #define DECLARE_SECURE_SVC(_name, _id, _fn) \ 26 .id = _id, \
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/u-boot/drivers/clk/stm32/ |
H A D | clk-stm32-core.h | 224 #define STM32_GATE(_id, _name, _parent, _flags, _gate_id, _sec_id) \ 226 .id = _id, \ 243 #define STM32_COMPOSITE(_id, _name, _flags, _sec_id, \ 246 .id = _id, \ 258 #define STM32_COMPOSITE_NOMUX(_id, _name, _parent, _flags, _sec_id, \ 261 .id = _id, \
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/u-boot/tools/ |
H A D | imagetool.h | 309 _id, \ 322 static struct image_type_params __cat(image_type_, _id) = \ 337 __cat(image_type_ptr_, _id) = &__cat(image_type_, _id)
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/u-boot/drivers/clk/microchip/ |
H A D | mpfs_clk_msspll.c | 77 #define CLK_PLL(_id, _name, _shift, _width, _reg_offset, _flags) { \ 78 .id = _id, \
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/u-boot/arch/arm/include/asm/arch-rockchip/ |
H A D | clock.h | 47 #define PLL(_type, _id, _con, _mode, _mshift, \ 50 .id = _id, \
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/u-boot/drivers/clk/mtmips/ |
H A D | clk-mt7621.c | 74 #define CLK_MAP(_id, _cg, _src) \ 75 [_id] = { .cgbit = (_cg), .clksrc = (_src) } 77 #define CLK_MAP_SRC(_id, _src) \ 78 [_id] = { .cgbit = UINT32_MAX, .clksrc = (_src) }
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