Searched refs:SRDS_PLLCR0_RFCK_SEL_MASK (Results 1 - 6 of 6) sorted by relevance

/u-boot/board/freescale/p2041rdb/
H A Dp2041rdb.c208 expected &= SRDS_PLLCR0_RFCK_SEL_MASK;
/u-boot/board/keymile/kmcent2/
H A Dkmcent2.c232 if ((actual & SRDS_PLLCR0_RFCK_SEL_MASK) != EXPECTED_SRDS_RFCK) {
/u-boot/arch/arm/include/asm/arch-ls102xa/
H A Dimmap_ls102xa.h306 #define SRDS_PLLCR0_RFCK_SEL_MASK 0x70000000 macro
/u-boot/arch/powerpc/cpu/mpc85xx/
H A Dfsl_corenet_serdes.c405 SRDS_PLLCR0_RFCK_SEL_MASK, rfck_sel);
/u-boot/arch/arm/include/asm/arch-fsl-layerscape/
H A Dimmap_lsch2.h542 #define SRDS_PLLCR0_RFCK_SEL_MASK 0x70000000 macro
/u-boot/arch/powerpc/include/asm/
H A Dimmap_85xx.h2191 #define SRDS_PLLCR0_RFCK_SEL_MASK 0x70000000 macro
2274 #define SRDS_PLLCR0_RFCK_SEL_MASK 0x70000000 macro

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