Searched refs:SRDS_PLLCR0_RFCK_SEL_125 (Results 1 - 8 of 8) sorted by relevance

/u-boot/board/freescale/p2041rdb/
H A Dp2041rdb.c175 {0, SRDS_PLLCR0_RFCK_SEL_100, SRDS_PLLCR0_RFCK_SEL_125},
177 SRDS_PLLCR0_RFCK_SEL_125}
/u-boot/arch/arm/cpu/armv7/ls102xa/
H A Dfsl_ls1_serdes.c125 case SRDS_PLLCR0_RFCK_SEL_125:
/u-boot/arch/powerpc/cpu/mpc85xx/
H A Dfsl_corenet_serdes.c396 rfck_sel = SRDS_PLLCR0_RFCK_SEL_125;
878 case SRDS_PLLCR0_RFCK_SEL_125:
H A Dfsl_corenet2_serdes.c388 case SRDS_PLLCR0_RFCK_SEL_125:
/u-boot/arch/arm/include/asm/arch-ls102xa/
H A Dimmap_ls102xa.h308 #define SRDS_PLLCR0_RFCK_SEL_125 0x10000000 macro
/u-boot/arch/arm/cpu/armv8/fsl-layerscape/
H A Dfsl_lsch2_serdes.c92 case SRDS_PLLCR0_RFCK_SEL_125:
/u-boot/arch/arm/include/asm/arch-fsl-layerscape/
H A Dimmap_lsch2.h544 #define SRDS_PLLCR0_RFCK_SEL_125 0x10000000 macro
/u-boot/arch/powerpc/include/asm/
H A Dimmap_85xx.h2193 #define SRDS_PLLCR0_RFCK_SEL_125 0x10000000 macro
2277 #define SRDS_PLLCR0_RFCK_SEL_125 0x10000000 macro

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