| /u-boot/arch/arm/mach-renesas/include/mach/ |
| H A D | rzg2l.h | 10 #define GICD_BASE 0x11900000 macro
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| H A D | rcar-gen4-base.h | 42 #define GICD_BASE 0xF1000000 macro
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| /u-boot/arch/arm/include/asm/arch-tegra186/ |
| H A D | tegra.h | 9 #define GICD_BASE 0x03881000 /* Generic Int Cntrlr Distrib */ macro
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| /u-boot/include/configs/ |
| H A D | px30_common.h | 13 #define GICD_BASE 0xff131000 macro
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| H A D | rv1126_common.h | 16 #define GICD_BASE 0xfeff1000 macro
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| H A D | hikey960.h | 24 #define GICD_BASE 0xe82b1000 macro
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| H A D | thunderx_88xx.h | 23 #define GICD_BASE (0x801000000000) macro
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| H A D | rcar-gen3-common.h | 17 #define GICD_BASE 0xF1010000 macro
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| H A D | hikey.h | 30 #define GICD_BASE 0xf6801000 macro
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| H A D | meson64.h | 12 #define GICD_BASE 0xffc01000 macro
15 #define GICD_BASE 0xff901000 macro
18 #define GICD_BASE 0xc4301000 macro
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| H A D | presidio_asic.h | 15 /* note: arch/arm/cpu/armv8/start.S which references GICD_BASE/GICC_BASE
18 #define GICD_BASE 0xf7011000 macro
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| H A D | vexpress_aemv8.h | 74 #define GICD_BASE (V2M_PA_BASE + 0x2f000000) macro
79 #define GICD_BASE (0x2C010000) macro
82 #define GICD_BASE (V2M_PA_BASE + 0x2f000000) macro
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| H A D | xilinx_versal_net.h | 19 #define GICD_BASE 0xe2000000 macro
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| H A D | xilinx_versal.h | 14 #define GICD_BASE 0xF9000000 macro
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| H A D | xilinx_zynqmp.h | 14 #define GICD_BASE 0xF9010000 macro
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| /u-boot/arch/arm/include/asm/arch-tegra210/ |
| H A D | tegra.h | 10 #define GICD_BASE 0x50041000 /* Generic Int Cntrlr Distrib */ macro
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| /u-boot/arch/arm/mach-renesas/ |
| H A D | lowlevel_init_gen3.S | 47 ldr x0, =GICD_BASE
54 ldr x0, =GICD_BASE
61 ldr x0, =GICD_BASE
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| /u-boot/arch/arm/mach-socfpga/ |
| H A D | lowlevel_init_soc64.S | 27 ldr x0, =GICD_BASE
34 ldr x0, =GICD_BASE
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| /u-boot/board/cortina/presidio-asic/ |
| H A D | lowlevel_init.S | 37 ldr x0, =GICD_BASE
44 ldr x0, =GICD_BASE
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| /u-boot/arch/arm/include/asm/arch-fsl-layerscape/ |
| H A D | config.h | 41 #define GICD_BASE 0x06000000 macro
115 #define GICD_BASE 0x06000000 macro
152 #define GICD_BASE 0x06000000 macro
184 #define GICD_BASE 0x06000000 macro
222 #define GICD_BASE 0x01401000 macro
248 #define GICD_BASE 0x01401000 macro
264 #define GICD_BASE 0x01410000 macro
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| /u-boot/arch/arm/mach-socfpga/include/mach/ |
| H A D | base_addr_soc64.h | 41 #define GICD_BASE 0x1d000000 macro
80 #define GICD_BASE 0xfffc1000 macro
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| /u-boot/board/renesas/falcon/ |
| H A D | falcon.c | 45 #define GICD_BASE 0xF1000000 macro
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| /u-boot/arch/arm/cpu/armv7/sunxi/ |
| H A D | psci.c | 25 #define GICD_BASE (SUNXI_GIC400_BASE + GIC_DIST_OFFSET) macro
335 writel(BIT(16) | 15, GICD_BASE + GICD_SGIR);
348 clrbits_le32(GICD_BASE + GICD_IGROUPRn, BIT(15));
351 writeb(0, GICD_BASE + GICD_IPRIORITYRn + 15);
|
| /u-boot/arch/arm/cpu/armv8/ |
| H A D | start.S | 294 ldr x0, =GICD_BASE
301 ldr x0, =GICD_BASE
348 ldr x0, =GICD_BASE
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| /u-boot/arch/arm/cpu/armv8/fsl-layerscape/ |
| H A D | lowlevel.S | 34 ldr x0, =GICD_BASE
|