1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Copyright 2016-2018, 2020 NXP 4 * Copyright 2015, Freescale Semiconductor 5 */ 6 7#ifndef _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_ 8#define _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_ 9 10#include <fsl_ddrc_version.h> 11 12#ifndef __ASSEMBLY__ 13#include <linux/bitops.h> 14#endif 15 16/* 17 * Reserve secure memory 18 * To be aligned with MMU block size 19 */ 20#define CFG_SYS_MEM_RESERVE_SECURE (66 * 1024 * 1024) /* 66MB */ 21#define SPL_TLB_SETBACK 0x1000000 /* 16MB under effective memory top */ 22 23#ifdef CONFIG_ARCH_LS2080A 24#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 } 25#define SRDS_MAX_LANES 8 26#define CFG_SYS_PAGE_SIZE 0x10000 27#ifndef L1_CACHE_BYTES 28#define L1_CACHE_SHIFT 6 29#define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT) 30#endif 31 32#define CFG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */ 33#define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */ 34#define CFG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */ 35 36/* DDR */ 37#define CFG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) 38#define CFG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE 39 40/* Generic Interrupt Controller Definitions */ 41#define GICD_BASE 0x06000000 42#define GICR_BASE 0x06100000 43 44/* SMMU Defintions */ 45#define SMMU_BASE 0x05000000 /* GR0 Base */ 46 47/* Cache Coherent Interconnect */ 48#define CCI_MN_BASE 0x04000000 49#define CCI_MN_RNF_NODEID_LIST 0x180 50#define CCI_MN_DVM_DOMAIN_CTL 0x200 51#define CCI_MN_DVM_DOMAIN_CTL_SET 0x210 52 53#define CCI_HN_F_0_BASE (CCI_MN_BASE + 0x200000) 54#define CCI_HN_F_1_BASE (CCI_MN_BASE + 0x210000) 55#define CCN_HN_F_SAM_CTL 0x8 /* offset on base HN_F base */ 56#define CCN_HN_F_SAM_NODEID_MASK 0x7f 57#define CCN_HN_F_SAM_NODEID_DDR0 0x4 58#define CCN_HN_F_SAM_NODEID_DDR1 0xe 59 60#define CCI_RN_I_0_BASE (CCI_MN_BASE + 0x800000) 61#define CCI_RN_I_2_BASE (CCI_MN_BASE + 0x820000) 62#define CCI_RN_I_6_BASE (CCI_MN_BASE + 0x860000) 63#define CCI_RN_I_12_BASE (CCI_MN_BASE + 0x8C0000) 64#define CCI_RN_I_16_BASE (CCI_MN_BASE + 0x900000) 65#define CCI_RN_I_20_BASE (CCI_MN_BASE + 0x940000) 66 67#define CCI_S0_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x10) 68#define CCI_S1_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x110) 69#define CCI_S2_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x210) 70 71#define CCI_AUX_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x0500) 72 73/* TZ Protection Controller Definitions */ 74#define TZPC_BASE 0x02200000 75#define TZPCR0SIZE_BASE (TZPC_BASE) 76#define TZPCDECPROT_0_STAT_BASE (TZPC_BASE + 0x800) 77#define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804) 78#define TZPCDECPROT_0_CLR_BASE (TZPC_BASE + 0x808) 79#define TZPCDECPROT_1_STAT_BASE (TZPC_BASE + 0x80C) 80#define TZPCDECPROT_1_SET_BASE (TZPC_BASE + 0x810) 81#define TZPCDECPROT_1_CLR_BASE (TZPC_BASE + 0x814) 82#define TZPCDECPROT_2_STAT_BASE (TZPC_BASE + 0x818) 83#define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C) 84#define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820) 85 86#define DCSR_CGACRE5 0x700070914ULL 87#define EPU_EPCMPR5 0x700060914ULL 88#define EPU_EPCCR5 0x700060814ULL 89#define EPU_EPSMCR5 0x700060228ULL 90#define EPU_EPECR5 0x700060314ULL 91#define EPU_EPCTR5 0x700060a14ULL 92#define EPU_EPGCR 0x700060000ULL 93 94#elif defined(CONFIG_ARCH_LS1088A) 95#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 } 96#define CFG_SYS_PAGE_SIZE 0x10000 97 98#define SRDS_MAX_LANES 4 99#define SRDS_BITS_PER_LANE 4 100 101/* TZ Protection Controller Definitions */ 102#define TZPC_BASE 0x02200000 103#define TZPCR0SIZE_BASE (TZPC_BASE) 104#define TZPCDECPROT_0_STAT_BASE (TZPC_BASE + 0x800) 105#define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804) 106#define TZPCDECPROT_0_CLR_BASE (TZPC_BASE + 0x808) 107#define TZPCDECPROT_1_STAT_BASE (TZPC_BASE + 0x80C) 108#define TZPCDECPROT_1_SET_BASE (TZPC_BASE + 0x810) 109#define TZPCDECPROT_1_CLR_BASE (TZPC_BASE + 0x814) 110#define TZPCDECPROT_2_STAT_BASE (TZPC_BASE + 0x818) 111#define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C) 112#define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820) 113 114/* Generic Interrupt Controller Definitions */ 115#define GICD_BASE 0x06000000 116#define GICR_BASE 0x06100000 117 118/* SMMU Defintions */ 119#define SMMU_BASE 0x05000000 /* GR0 Base */ 120 121/* DDR */ 122#define CFG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) 123#define CFG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE 124 125/* DCFG - GUR */ 126#define CFG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */ 127#define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */ 128#define CFG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */ 129 130/* LX2160A/LX2162A Soc Support */ 131#elif defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A) 132#define TZPC_BASE 0x02200000 133#define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804) 134#define SRDS_MAX_LANES 8 135#ifndef L1_CACHE_BYTES 136#define L1_CACHE_SHIFT 6 137#define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT) 138#endif 139#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1, 4, 4, 4, 4 } 140 141#define CFG_SYS_PAGE_SIZE 0x10000 142 143#define CFG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */ 144#define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */ 145#define CFG_SYS_FSL_OCRAM_SIZE 0x00040000 /* Real size 256K */ 146 147/* DDR */ 148#define CFG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) 149#define CFG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE 150 151/* Generic Interrupt Controller Definitions */ 152#define GICD_BASE 0x06000000 153#define GICR_BASE 0x06200000 154 155/* SMMU Definitions */ 156#define SMMU_BASE 0x05000000 /* GR0 Base */ 157 158/* DCFG - GUR */ 159 160#elif defined(CONFIG_ARCH_LS1028A) 161#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 } 162 163/* TZ Protection Controller Definitions */ 164#define TZPC_BASE 0x02200000 165#define TZPCR0SIZE_BASE (TZPC_BASE) 166#define TZPCDECPROT_0_STAT_BASE (TZPC_BASE + 0x800) 167#define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804) 168#define TZPCDECPROT_0_CLR_BASE (TZPC_BASE + 0x808) 169#define TZPCDECPROT_1_STAT_BASE (TZPC_BASE + 0x80C) 170#define TZPCDECPROT_1_SET_BASE (TZPC_BASE + 0x810) 171#define TZPCDECPROT_1_CLR_BASE (TZPC_BASE + 0x814) 172#define TZPCDECPROT_2_STAT_BASE (TZPC_BASE + 0x818) 173#define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C) 174#define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820) 175 176#define SRDS_MAX_LANES 4 177#define SRDS_BITS_PER_LANE 4 178 179#define CFG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */ 180#define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M */ 181#define CFG_SYS_FSL_OCRAM_SIZE 0x00040000 /* Real size 256K */ 182 183/* Generic Interrupt Controller Definitions */ 184#define GICD_BASE 0x06000000 185#define GICR_BASE 0x06040000 186 187/* SMMU Definitions */ 188#define SMMU_BASE 0x05000000 /* GR0 Base */ 189 190/* DDR */ 191#define CFG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) 192#define CFG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE 193 194/* SEC */ 195 196/* DCFG - GUR */ 197 198#elif defined(CONFIG_FSL_LSCH2) 199#define CFG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */ 200#define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */ 201#define CFG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */ 202 203#define DCSR_DCFG_SBEESR2 0x20140534 204#define DCSR_DCFG_MBEESR2 0x20140544 205 206/* SoC related */ 207#ifdef CONFIG_ARCH_LS1043A 208#define CFG_SYS_NUM_FMAN 1 209#define CFG_SYS_NUM_FM1_DTSEC 7 210#define CFG_SYS_NUM_FM1_10GEC 1 211#define CFG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) 212#define CFG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE 213 214#define QE_MURAM_SIZE 0x6000UL 215#define MAX_QE_RISC 1 216#define QE_NUM_OF_SNUM 28 217 218/* SMMU Defintions */ 219#define SMMU_BASE 0x09000000 220 221/* Generic Interrupt Controller Definitions */ 222#define GICD_BASE 0x01401000 223#define GICC_BASE 0x01402000 224#define GICH_BASE 0x01404000 225#define GICV_BASE 0x01406000 226#define GICD_SIZE 0x1000 227#define GICC_SIZE 0x2000 228#define GICH_SIZE 0x2000 229#define GICV_SIZE 0x2000 230#ifdef CONFIG_HAS_FEATURE_GIC64K_ALIGN 231#define GICD_BASE_64K 0x01410000 232#define GICC_BASE_64K 0x01420000 233#define GICH_BASE_64K 0x01440000 234#define GICV_BASE_64K 0x01460000 235#define GICD_SIZE_64K 0x10000 236#define GICC_SIZE_64K 0x20000 237#define GICH_SIZE_64K 0x20000 238#define GICV_SIZE_64K 0x20000 239#endif 240 241#define DCFG_CCSR_SVR 0x1ee00a4 242#define REV1_0 0x10 243#define REV1_1 0x11 244#define GIC_ADDR_BIT 31 245#define SCFG_GIC400_ALIGN 0x1570188 246 247#elif defined(CONFIG_ARCH_LS1012A) 248#define GICD_BASE 0x01401000 249#define GICC_BASE 0x01402000 250#define CFG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) 251#define CFG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE 252 253#elif defined(CONFIG_ARCH_LS1046A) 254#define CFG_SYS_NUM_FMAN 1 255#define CFG_SYS_NUM_FM1_DTSEC 8 256#define CFG_SYS_NUM_FM1_10GEC 2 257#define CFG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) 258#define CFG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE 259 260/* SMMU Defintions */ 261#define SMMU_BASE 0x09000000 262 263/* Generic Interrupt Controller Definitions */ 264#define GICD_BASE 0x01410000 265#define GICC_BASE 0x01420000 266#else 267#error SoC not defined 268#endif 269#endif 270 271#endif /* _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_ */ 272