1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * board/renesas/falcon/falcon.c
4 *     This file is Falcon board support.
5 *
6 * Copyright (C) 2020 Renesas Electronics Corp.
7 */
8
9#include <asm/arch/renesas.h>
10#include <asm/arch/sys_proto.h>
11#include <asm/global_data.h>
12#include <asm/io.h>
13#include <asm/mach-types.h>
14#include <asm/processor.h>
15#include <linux/errno.h>
16#include <asm/system.h>
17#include <asm/u-boot.h>
18
19DECLARE_GLOBAL_DATA_PTR;
20
21#define CPGWPR		0xE6150000
22#define CPGWPCR		0xE6150004
23
24#define EXTAL_CLK	16666600u
25#define CNTCR_BASE	0xE6080000
26#define CNTFID0		(CNTCR_BASE + 0x020)
27#define CNTCR_EN	BIT(0)
28
29static void init_generic_timer(void)
30{
31	u32 freq;
32
33	/* Set frequency data in CNTFID0 */
34	freq = EXTAL_CLK;
35
36	/* Update memory mapped and register based freqency */
37	asm volatile ("msr cntfrq_el0, %0" :: "r" (freq));
38	writel(freq, CNTFID0);
39
40	/* Enable counter */
41	setbits_le32(CNTCR_BASE, CNTCR_EN);
42}
43
44/* Distributor Registers */
45#define GICD_BASE	0xF1000000
46
47/* ReDistributor Registers for Control and Physical LPIs */
48#define GICR_LPI_BASE	0xF1060000
49#define GICR_WAKER	0x0014
50#define GICR_PWRR	0x0024
51#define GICR_LPI_WAKER	(GICR_LPI_BASE + GICR_WAKER)
52#define GICR_LPI_PWRR	(GICR_LPI_BASE + GICR_PWRR)
53
54/* ReDistributor Registers for SGIs and PPIs */
55#define GICR_SGI_BASE	0xF1070000
56#define GICR_IGROUPR0	0x0080
57
58static void init_gic_v3(void)
59{
60	 /* GIC v3 power on */
61	writel(0x00000002, (GICR_LPI_PWRR));
62
63	/* Wait till the WAKER_CA_BIT changes to 0 */
64	writel(readl(GICR_LPI_WAKER) & ~0x00000002, (GICR_LPI_WAKER));
65	while (readl(GICR_LPI_WAKER) & 0x00000004)
66		;
67
68	writel(0xffffffff, GICR_SGI_BASE + GICR_IGROUPR0);
69}
70
71void s_init(void)
72{
73	if (current_el() == 3)
74		init_generic_timer();
75}
76
77int board_early_init_f(void)
78{
79	/* Unlock CPG access */
80	writel(0x5A5AFFFF, CPGWPR);
81	writel(0xA5A50000, CPGWPCR);
82
83	return 0;
84}
85
86#define RST_BASE	0xE6160000 /* Domain0 */
87#define RST_WDTRSTCR	(RST_BASE + 0x10)
88#define RST_RWDT	0xA55A8002
89
90int board_init(void)
91{
92	/* address of boot parameters */
93	gd->bd->bi_boot_params = CONFIG_TEXT_BASE + 0x50000;
94
95	if (current_el() == 3) {
96		init_gic_v3();
97
98		/* Enable RWDT reset */
99		writel(RST_RWDT, RST_WDTRSTCR);
100	}
101
102	return 0;
103}
104