| /u-boot/arch/arm/include/asm/arch-rockchip/ |
| H A D | cru_rk3188.h | 164 DPLL_MODE_MASK = 3, enumerator in enum:__anon83
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| H A D | cru_rk3036.h | 91 DPLL_MODE_MASK = 1 << DPLL_MODE_SHIFT, enumerator in enum:__anon27
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| H A D | cru_rk3288.h | 198 DPLL_MODE_MASK = CRU_MODE_MASK << DPLL_MODE_SHIFT, enumerator in enum:__anon10
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| H A D | cru_rk322x.h | 98 DPLL_MODE_MASK = 1 << DPLL_MODE_SHIFT, enumerator in enum:__anon29
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| H A D | cru_rk3128.h | 104 DPLL_MODE_MASK = 1 << DPLL_MODE_SHIFT, enumerator in enum:__anon28
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| H A D | cru_rk3308.h | 133 DPLL_MODE_MASK = 3 << DPLL_MODE_SHIFT, enumerator in enum:__anon2
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| H A D | cru_px30.h | 154 DPLL_MODE_MASK = 3 << DPLL_MODE_SHIFT, enumerator in enum:__anon1
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| /u-boot/drivers/clk/rockchip/ |
| H A D | clk_rk322x.c | 187 0xff, APLL_MODE_MASK, DPLL_MODE_MASK, 0xff,
345 rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK,
349 rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK,
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| H A D | clk_rk3066.c | 145 rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK,
155 rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK,
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| H A D | clk_rk3188.c | 153 rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK << DPLL_MODE_SHIFT,
163 rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK << DPLL_MODE_SHIFT,
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| H A D | clk_rk3036.c | 185 0xffffffff, APLL_MODE_MASK, DPLL_MODE_MASK, 0xffffffff,
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| H A D | clk_rk3288.c | 211 rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK,
221 rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK,
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| H A D | clk_rk3128.c | 253 0xff, APLL_MODE_MASK, DPLL_MODE_MASK, CPLL_MODE_MASK,
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| H A D | clk_px30.c | 88 APLL_MODE_MASK, DPLL_MODE_MASK, CPLL_MODE_MASK,
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| /u-boot/arch/arm/mach-rockchip/rk3036/ |
| H A D | sdram_rk3036.c | 332 rk_clrsetreg(&priv->cru->cru_mode_con, DPLL_MODE_MASK,
351 rk_clrsetreg(&priv->cru->cru_mode_con, DPLL_MODE_MASK,
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