Searched refs:CFG_SYS_DDR_TIMING_0 (Results 1 - 10 of 10) sorted by relevance

/u-boot/include/configs/
H A Dsocrates.h55 #define CFG_SYS_DDR_TIMING_0 0x00260802 macro
H A Dcmpcpro.h28 #define CFG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) | \ macro
H A DMPC837XERDB.h69 #define CFG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ macro
H A Dp1_p2_rdb_pc.h151 #define CFG_SYS_DDR_TIMING_0 0x00330004 macro
/u-boot/board/socrates/
H A Dsdram.c39 ddr->timing_cfg_0 = CFG_SYS_DDR_TIMING_0;
/u-boot/board/gdsys/mpc8308/
H A Dsdram.c55 out_be32(&im->ddr.timing_cfg_0, CFG_SYS_DDR_TIMING_0);
/u-boot/board/keymile/km83xx/
H A Dkm83xx.c44 #define CFG_SYS_DDR_TIMING_0 (\ macro
79 #define CFG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ macro
218 out_be32(&im->ddr.timing_cfg_0, CFG_SYS_DDR_TIMING_0);
/u-boot/board/freescale/mpc837xerdb/
H A Dmpc837xerdb.c116 im->ddr.timing_cfg_0 = CFG_SYS_DDR_TIMING_0;
/u-boot/board/freescale/p1_p2_rdb_pc/
H A Dddr.c221 .timing_cfg_0 = CFG_SYS_DDR_TIMING_0,
/u-boot/board/cssi/cmpcpro/
H A Dcmpcpro.c308 out_be32(&im->ddr.timing_cfg_0, CFG_SYS_DDR_TIMING_0);

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