Searched refs:BIT (Results 1 - 25 of 383) sorted by relevance

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/seL4-test-master/kernel/src/arch/x86/64/model/
H A Dstatedata.c10 pml4e_t x64KSKernelPML4[BIT(PML4_INDEX_BITS)] ALIGN(BIT(seL4_PML4Bits)) VISIBLE;
11 pdpte_t x64KSKernelPDPT[BIT(PDPT_INDEX_BITS)] ALIGN(BIT(seL4_PDPTBits));
13 pde_t x64KSKernelPD[BIT(PD_INDEX_BITS)] ALIGN(BIT(seL4_PageDirBits));
15 pde_t x64KSKernelPDs[BIT(PDPT_INDEX_BITS)][BIT(PD_INDEX_BITS)] ALIGN(BIT(seL4_PageDirBits));
17 pte_t x64KSKernelPT[BIT(PT_INDEX_BIT
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/seL4-test-master/kernel/include/arch/x86/arch/machine/
H A Dcpu_registers.h9 #define CR0_MONITOR_COPROC BIT(1) /* Trap on FPU "WAIT" commands. */
10 #define CR0_EMULATION BIT(2) /* Enable OS emulation of FPU. */
11 #define CR0_TASK_SWITCH BIT(3) /* Trap on any FPU usage, for lazy FPU. */
12 #define CR0_NUMERIC_ERROR BIT(5) /* Internally handle FPU problems. */
13 #define CR0_WRITE_PROTECT BIT(16) /* Write protection in supervisor mode. */
14 #define CR4_PCE BIT(8) /* Performance-Monitoring Counter enable. */
15 #define CR4_OSFXSR BIT(9) /* Enable SSE et. al. features. */
16 #define CR4_OSXMMEXCPT BIT(10) /* Enable SSE exceptions. */
17 #define CR4_OSXSAVE BIT(18) /* Enavle XSAVE feature set */
18 #define CR4_VMXE BIT(1
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/seL4-test-master/projects/util_libs/libplatsupport/plat_include/am335x/platsupport/plat/
H A Di2c.h71 #define IRQSTATUS_XDR BIT(14)
72 #define IRQSTATUS_RDR BIT(13)
73 #define IRQSTATUS_BB BIT(12)
74 #define IRQSTATUS_ROVR BIT(11)
75 #define IRQSTATUS_XUDF BIT(10)
76 #define IRQSTATUS_AAS BIT(9)
77 #define IRQSTATUS_BF BIT(8)
78 #define IRQSTATUS_AERR BIT(7)
79 #define IRQSTATUS_STC BIT(6)
80 #define IRQSTATUS_GC BIT(
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/seL4-test-master/tools/seL4/elfloader-tool/src/arch-arm/32/
H A Dstructures.c12 uint32_t _boot_pd[BIT(PD_BITS)] ALIGN(BIT(PD_SIZE_BITS));
13 uint32_t _boot_pt[BIT(PT_BITS)] ALIGN(BIT(PT_SIZE_BITS));
16 uint64_t _lpae_boot_pgd[BIT(HYP_PGD_BITS)] ALIGN(BIT(HYP_PGD_SIZE_BITS));
17 uint64_t _lpae_boot_pmd[BIT(HYP_PGD_BITS + HYP_PMD_BITS)] ALIGN(BIT(HYP_PMD_SIZE_BITS));
H A Dmmu.c27 | BIT(10) /* kernel-only access */
28 | BIT(1); /* 1M section */
35 | BIT(10) /* kernel-only access */
36 | BIT(1); /* 1M section */
42 | BIT(9)
43 | BIT(0); /* page table */
48 | BIT(4) /* kernel-only access */
49 | BIT(1); /* 4K page */
66 | BIT(1) /* Page table */
67 | BIT(
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/seL4-test-master/projects/sel4test/apps/sel4test-tests/sel4_arch/aarch32/
H A Darch_frame_type.h22 { seL4_ARM_SectionObject, BIT(24), 20, },
23 { seL4_ARM_LargePageObject, BIT(24) + BIT(20), 16, },
24 { seL4_ARM_SmallPageObject, BIT(24) + BIT(20) + BIT(16), seL4_PageBits, },
/seL4-test-master/projects/sel4test/apps/sel4test-tests/sel4_arch/arm_hyp/
H A Darch_frame_type.h22 { seL4_ARM_SectionObject, BIT(25), 21, },
23 { seL4_ARM_LargePageObject, BIT(25) + BIT(21), 16, },
24 { seL4_ARM_SmallPageObject, BIT(25) + BIT(21) + BIT(16), seL4_PageBits, },
/seL4-test-master/tools/seL4/elfloader-tool/src/arch-arm/64/
H A Dstructures.c12 uint64_t _boot_pgd_up[BIT(PGD_BITS)] ALIGN(BIT(PGD_SIZE_BITS));
13 uint64_t _boot_pud_up[BIT(PUD_BITS)] ALIGN(BIT(PUD_SIZE_BITS));
14 uint64_t _boot_pmd_up[BIT(PMD_BITS)] ALIGN(BIT(PMD_SIZE_BITS));
17 uint64_t _boot_pgd_down[BIT(PGD_BITS)] ALIGN(BIT(PGD_SIZE_BITS));
18 uint64_t _boot_pud_down[BIT(PUD_BITS)] ALIGN(BIT(PUD_SIZE_BIT
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H A Dmmu.c28 _boot_pgd_down[0] = ((uintptr_t)_boot_pud_down) | BIT(1) | BIT(0); /* its a page table */
30 for (i = 0; i < BIT(PUD_BITS); i++) {
32 | BIT(10) /* access flag */
34 | BIT(0); /* 1G block */
38 = ((uintptr_t)_boot_pud_up) | BIT(1) | BIT(0); /* its a page table */
41 = ((uintptr_t)_boot_pmd_up) | BIT(1) | BIT(0); /* its a page table */
48 for (i = GET_PMD_INDEX(first_vaddr); i < BIT(PMD_BIT
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/seL4-test-master/kernel/src/arch/arm/32/model/
H A Dstatedata.c19 word_t armKSGlobalsFrame[BIT(ARMSmallPageBits) / sizeof(word_t)]
20 ALIGN_BSS(BIT(ARMSmallPageBits));
24 asid_pool_t *armKSASIDTable[BIT(asidHighBits)];
27 asid_t armKSHWASIDTable[BIT(hwASIDBits)];
32 pde_t armKSGlobalPD[BIT(PD_INDEX_BITS)] ALIGN_BSS(BIT(seL4_PageDirBits));
35 pte_t armKSGlobalPT[BIT(PT_INDEX_BITS)] ALIGN_BSS(BIT(seL4_PageTableBits));
38 pte_t armKSGlobalLogPT[BIT(PT_INDEX_BITS)] ALIGN_BSS(BIT(seL4_PageTableBit
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/seL4-test-master/kernel/include/arch/x86/arch/64/mode/model/
H A Dstatedata.h14 extern pml4e_t x64KSKernelPML4[BIT(PML4_INDEX_BITS)] VISIBLE;
15 extern pdpte_t x64KSKernelPDPT[BIT(PDPT_INDEX_BITS)];
17 extern pde_t x64KSKernelPD[BIT(PD_INDEX_BITS)];
19 extern pde_t x64KSKernelPDs[BIT(PDPT_INDEX_BITS)][BIT(PD_INDEX_BITS)];
21 extern pte_t x64KSKernelPT[BIT(PT_INDEX_BITS)];
24 extern pml4e_t x64KSSKIMPML4[BIT(PML4_INDEX_BITS)] ALIGN(BIT(seL4_PML4Bits));
25 extern pdpte_t x64KSSKIMPDPT[BIT(PDPT_INDEX_BITS)] ALIGN(BIT(seL4_PDPTBit
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/seL4-test-master/kernel/src/arch/x86/32/model/
H A Dstatedata.c14 pde_t ia32KSGlobalPD[BIT(PD_INDEX_BITS)] ALIGN(BIT(seL4_PageDirBits));
15 pte_t ia32KSGlobalPT[BIT(PT_INDEX_BITS)] ALIGN(BIT(seL4_PageTableBits));
18 pte_t ia32KSGlobalLogPT[BIT(PT_INDEX_BITS)] ALIGN(BIT(seL4_PageTableBits));
/seL4-test-master/kernel/include/arch/arm/arch/32/mode/model/
H A Dstatedata.h16 extern word_t armKSGlobalsFrame[BIT(ARMSmallPageBits) / sizeof(word_t)] VISIBLE;
18 extern asid_pool_t *armKSASIDTable[BIT(asidHighBits)] VISIBLE;
19 extern asid_t armKSHWASIDTable[BIT(hwASIDBits)] VISIBLE;
23 extern pde_t armKSGlobalPD[BIT(PD_INDEX_BITS)] VISIBLE;
24 extern pte_t armKSGlobalPT[BIT(PT_INDEX_BITS)] VISIBLE;
27 extern pte_t armKSGlobalLogPT[BIT(PT_INDEX_BITS)] VISIBLE;
31 extern pdeS1_t armHSGlobalPGD[BIT(PGD_INDEX_BITS)] VISIBLE;
32 extern pdeS1_t armHSGlobalPD[BIT(PT_INDEX_BITS)] VISIBLE;
33 extern pteS1_t armHSGlobalPT[BIT(PT_INDEX_BITS)] VISIBLE;
34 extern pde_t armUSGlobalPD[BIT(PD_INDEX_BIT
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/seL4-test-master/kernel/src/arch/arm/64/model/
H A Dstatedata.c21 asid_pool_t *armKSASIDTable[BIT(asidHighBits)];
85 vspace_root_t armKSGlobalUserVSpace[BIT(seL4_VSpaceIndexBits)] ALIGN_BSS(BIT(seL4_VSpaceBits));
86 pgde_t armKSGlobalKernelPGD[BIT(PGD_INDEX_BITS)] ALIGN_BSS(BIT(PGD_SIZE_BITS));
88 pude_t armKSGlobalKernelPUD[BIT(PUD_INDEX_BITS)] ALIGN_BSS(BIT(seL4_PUDBits));
89 pde_t armKSGlobalKernelPDs[BIT(PUD_INDEX_BITS)][BIT(PD_INDEX_BITS)] ALIGN_BSS(BIT(seL4_PageDirBit
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/seL4-test-master/projects/util_libs/libplatsupport/plat_include/odroidc2/platsupport/plat/
H A Dmeson_timer.h28 #define TIMER_D_EN BIT(19)
29 #define TIMER_C_EN BIT(18)
30 #define TIMER_B_EN BIT(17)
31 #define TIMER_A_EN BIT(16)
32 #define TIMER_D_MODE BIT(15)
33 #define TIMER_C_MODE BIT(14)
34 #define TIMER_B_MODE BIT(13)
35 #define TIMER_A_MODE BIT(12)
37 #define TIMER_I_EN BIT(19)
38 #define TIMER_H_EN BIT(1
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/seL4-test-master/kernel/include/arch/arm/arch/64/mode/model/
H A Dstatedata.h20 extern asid_pool_t *armKSASIDTable[BIT(asidHighBits)] VISIBLE;
24 extern vspace_root_t armKSGlobalUserVSpace[BIT(seL4_VSpaceIndexBits)] VISIBLE;
25 extern pgde_t armKSGlobalKernelPGD[BIT(PGD_INDEX_BITS)] VISIBLE;
27 extern pude_t armKSGlobalKernelPUD[BIT(PUD_INDEX_BITS)] VISIBLE;
28 extern pde_t armKSGlobalKernelPDs[BIT(PUD_INDEX_BITS)][BIT(PD_INDEX_BITS)] VISIBLE;
29 extern pte_t armKSGlobalKernelPT[BIT(PT_INDEX_BITS)] VISIBLE;
33 extern asid_t armKSHWASIDTable[BIT(hwASIDBits)] VISIBLE;
44 extern cte_t smmuStateSIDNode[BIT(SMMU_SID_CNODE_SLOT_BITS)];
46 extern cte_t smmuStateCBNode[BIT(SMMU_CB_CNODE_SLOT_BIT
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/seL4-test-master/projects/util_libs/libethdrivers/src/plat/tx2/uboot/
H A Ddwc_eth_qos.h77 #define EQOS_MAC_CONFIGURATION_GPSLCE BIT(23)
78 #define EQOS_MAC_CONFIGURATION_CST BIT(21)
79 #define EQOS_MAC_CONFIGURATION_ACS BIT(20)
80 #define EQOS_MAC_CONFIGURATION_WD BIT(19)
81 #define EQOS_MAC_CONFIGURATION_JD BIT(17)
82 #define EQOS_MAC_CONFIGURATION_JE BIT(16)
83 #define EQOS_MAC_CONFIGURATION_PS BIT(15)
84 #define EQOS_MAC_CONFIGURATION_FES BIT(14)
85 #define EQOS_MAC_CONFIGURATION_DM BIT(13)
86 #define EQOS_MAC_CONFIGURATION_TE BIT(
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/seL4-test-master/kernel/src/arch/riscv/model/
H A Dstatedata.c18 asid_pool_t *riscvKSASIDTable[BIT(asidHighBits)];
21 pte_t kernel_root_pageTable[BIT(PT_INDEX_BITS)] ALIGN_BSS(BIT(seL4_PageTableBits));
24 pte_t kernel_image_level2_pt[BIT(PT_INDEX_BITS)] ALIGN_BSS(BIT(seL4_PageTableBits));
25 pte_t kernel_image_level2_dev_pt[BIT(PT_INDEX_BITS)] ALIGN_BSS(BIT(seL4_PageTableBits));
27 pte_t kernel_image_level2_log_buffer_pt[BIT(PT_INDEX_BITS)] ALIGN_BSS(BIT(seL4_PageTableBits));
/seL4-test-master/projects/util_libs/libplatsupport/src/mach/zynq/
H A Dserial.c23 #define UART_CR_RXRES BIT( 0)
24 #define UART_CR_TXRES BIT( 1)
25 #define UART_CR_RXEN BIT( 2)
26 #define UART_CR_RXDIS BIT( 3)
27 #define UART_CR_TXEN BIT( 4)
28 #define UART_CR_TXDIS BIT( 5)
29 #define UART_CR_RSTTO BIT( 6)
30 #define UART_CR_STTBRK BIT( 7)
31 #define UART_CR_STPBRK BIT( 8)
33 #define UART_MR_CLKS BIT(
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/seL4-test-master/kernel/src/kernel/
H A Dstack.c10 char kernel_stack_alloc[CONFIG_MAX_NUM_NODES][BIT(CONFIG_KERNEL_STACK_BITS)];
/seL4-test-master/kernel/include/plat/pc99/plat/machine/
H A Ddevices.h13 #define PPTR_IOAPIC_START (PPTR_APIC + BIT(PAGE_BITS))
14 #define PPTR_DRHU_START (PPTR_IOAPIC_START + BIT(PAGE_BITS) * CONFIG_MAX_NUM_IOAPIC)
/seL4-test-master/kernel/include/arch/x86/arch/32/mode/model/
H A Dstatedata.h15 extern pde_t ia32KSGlobalPD[BIT(PD_INDEX_BITS)];
16 extern pte_t ia32KSGlobalPT[BIT(PT_INDEX_BITS)];
19 extern pte_t ia32KSGlobalLogPT[BIT(PT_INDEX_BITS)];
/seL4-test-master/kernel/include/arch/riscv/arch/model/
H A Dstatedata.h25 extern asid_pool_t *riscvKSASIDTable[BIT(asidHighBits)];
28 extern pte_t kernel_root_pageTable[BIT(PT_INDEX_BITS)] VISIBLE;
33 extern pte_t kernel_image_level2_pt[BIT(PT_INDEX_BITS)];
34 extern pte_t kernel_image_level2_dev_pt[BIT(PT_INDEX_BITS)];
36 extern pte_t kernel_image_level2_log_buffer_pt[BIT(PT_INDEX_BITS)];
/seL4-test-master/kernel/src/drivers/serial/
H A Dbcm2835-aux-uart.c27 #define MU_LSR_TXEMPTY BIT(5)
30 #define MU_LSR_TXIDLE BIT(6)
31 #define MU_LSR_RXOVERRUN BIT(1)
32 #define MU_LSR_DATAREADY BIT(0)
33 #define MU_LCR_DLAB BIT(7)
34 #define MU_LCR_BREAK BIT(6)
35 #define MU_LCR_DATASIZE BIT(0)
/seL4-test-master/kernel/src/arch/arm/armv/armv8-a/64/
H A Duser_access.c11 #define EL0VCTEN BIT(1)
12 #define EL0PCTEN BIT(0)
13 #define EL0VTEN BIT(8)
14 #define EL0PTEN BIT(9)
17 #define EL1PCEN BIT(1)
18 #define EL1PCTEN BIT(0)
20 #define PMUSERENR_EL0_EN BIT(0)

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