1/* 2 * Copyright 2019, Data61 3 * Commonwealth Scientific and Industrial Research Organisation (CSIRO) 4 * ABN 41 687 119 230. 5 * 6 * This software may be distributed and modified according to the terms of 7 * the BSD 2-Clause license. Note that NO WARRANTY is provided. 8 * See "LICENSE_BSD2.txt" for details. 9 * 10 * @TAG(DATA61_BSD) 11 */ 12 13#pragma once 14 15#include <utils/arith.h> 16 17enum i2c_id { 18 AM335X_I2C0, 19 AM335X_I2C1, 20 AM335X_I2C2, 21 NI2C 22}; 23 24#include <platsupport/i2c.h> 25 26#define AM335X_I2C0_PADDR 0x44e0b000 27#define AM335X_I2C1_PADDR 0x4802a000 28#define AM335X_I2C2_PADDR 0x4819c000 29 30#define AM335X_I2C0_IRQ 70 31#define AM335X_I2C1_IRQ 71 32#define AM335X_I2C2_IRQ 30 33 34#define AM335X_I2C_SCLK 48000000 35#define AM335X_I2C_MAX_FIFODEPTH 32 36 37/* OMAP4 I2C device registers */ 38#define OMAP4_I2C_REVNB_LO 0x0 39#define OMAP4_I2C_REVNB_HI 0x4 40#define OMAP4_I2C_SYSC 0x10 41#define OMAP4_I2C_IRQSTATUS_RAW 0x24 42#define OMAP4_I2C_IRQSTATUS 0x28 43#define OMAP4_I2C_IRQENABLE_SET 0x2C 44#define OMAP4_I2C_IRQENABLE_CLR 0x30 45#define OMAP4_I2C_WE 0x34 46#define OMAP4_I2C_DMARXENABLE_SET 0x38 47#define OMAP4_I2C_DMATXENABLE_SET 0x3C 48#define OMAP4_I2C_DMARXENABLE_CLR 0x40 49#define OMAP4_I2C_DMATXENABLE_CLR 0x44 50#define OMAP4_I2C_DMARXWAKE_EN 0x48 51#define OMAP4_I2C_DMATXWAKE_EN 0x4C 52#define OMAP4_I2C_SYSS 0x90 53#define OMAP4_I2C_BUF 0x94 54#define OMAP4_I2C_CNT 0x98 55#define OMAP4_I2C_DATA 0x9C 56#define OMAP4_I2C_CON 0xA4 57#define OMAP4_I2C_OA 0xA8 58#define OMAP4_I2C_SA 0xAC 59#define OMAP4_I2C_PSC 0xB0 60#define OMAP4_I2C_SCLL 0xB4 61#define OMAP4_I2C_SCLH 0xB8 62#define OMAP4_I2C_SYSTEST 0xBC 63#define OMAP4_I2C_BUFSTAT 0xC0 64#define OMAP4_I2C_OA1 0xC4 65#define OMAP4_I2C_OA2 0xC8 66#define OMAP4_I2C_OA3 0xCC 67#define OMAP4_I2C_ACTOA 0xD0 68#define OMAP4_I2C_SBLOCK 0xD4 69 70/* I2C_IRQSTATUS and I2C_IRQSTATUS_RAW fields */ 71#define IRQSTATUS_XDR BIT(14) 72#define IRQSTATUS_RDR BIT(13) 73#define IRQSTATUS_BB BIT(12) 74#define IRQSTATUS_ROVR BIT(11) 75#define IRQSTATUS_XUDF BIT(10) 76#define IRQSTATUS_AAS BIT(9) 77#define IRQSTATUS_BF BIT(8) 78#define IRQSTATUS_AERR BIT(7) 79#define IRQSTATUS_STC BIT(6) 80#define IRQSTATUS_GC BIT(5) 81#define IRQSTATUS_XRDY BIT(4) 82#define IRQSTATUS_RRDY BIT(3) 83#define IRQSTATUS_ARDY BIT(2) 84#define IRQSTATUS_NACK BIT(1) 85#define IRQSTATUS_AL BIT(0) 86 87/* I2C_IRQENABLE_SET fields */ 88#define IRQENABLE_XDR BIT(14) 89#define IRQENABLE_RDR BIT(13) 90/* no IRQENABLE_BB */ 91#define IRQENABLE_ROVR BIT(11) 92#define IRQENABLE_XUDF BIT(10) 93#define IRQENABLE_AAS BIT(9) 94#define IRQENABLE_BF BIT(8) 95#define IRQENABLE_AERR BIT(7) 96#define IRQENABLE_STC BIT(6) 97#define IRQENABLE_GC BIT(5) 98#define IRQENABLE_XRDY BIT(4) 99#define IRQENABLE_RRDY BIT(3) 100#define IRQENABLE_ARDY BIT(2) 101#define IRQENABLE_NACK BIT(1) 102#define IRQENABLE_AL BIT(0) 103 104/* I2C_BUF fields */ 105#define BUF_RXTRSH_OFFSET 8 106#define BUF_RDMA_EN BIT(15) 107#define BUF_RXFIFO_CLR BIT(14) 108#define BUF_RXTRSH_MASK (MASK(6) << BUF_RXTRSH_OFFSET) 109#define BUF_RXDMA_EN BIT(7) 110#define BUF_TXFIFO_CLR BIT(6) 111#define BUF_TXTRSH_MASK MASK(6) 112 113/* I2C_CON fields */ 114#define CON_I2C_EN BIT(15) 115/* bit 14 reserved */ 116#define CON_OPMODE (MASK(2) << 12) 117#define CON_STB BIT(11) 118#define CON_MST BIT(10) 119#define CON_TRX BIT(9) 120#define CON_XSA BIT(8) 121#define CON_XOA0 BIT(7) 122#define CON_XOA1 BIT(6) 123#define CON_XOA2 BIT(5) 124#define CON_XOA3 BIT(4) 125/* bits 2-3 reserved */ 126#define CON_STP BIT(1) 127#define CON_STT BIT(0) 128 129int omap4_i2c_init(void *vaddr, int irq_id, ps_io_ops_t *io_ops, i2c_bus_t *i2c_bus); 130