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a00c2c16 |
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17-Sep-2020 |
Curtis Millar <curtis.millar@data61.csiro.au> |
Make kernel log buffer derived from cmake config This removes the explicit CMake configuration for the kernel log buffer and replaces it with a #define that is enabled for the required configurations. Signed-off-by: Curtis Millar <curtis@curtism.me>
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512a0200 |
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19-Mar-2020 |
Qian Ge <qian.ge@data61.csiro.au> |
replacing all ifndef with pargma once All the kernel header files now use pargma once rather than the ifndef, as the pre-processed C files do not change while header files are protected with pargma once. This will also solve any naming issues caused by ifndef.
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79da0792 |
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01-Mar-2020 |
Gerwin Klein <gerwin.klein@data61.csiro.au> |
Convert license tags to SPDX identifiers This commit also converts our own copyright headers to directly use SPDX, but leaves all other copyright header intact, only adding the SPDX ident. As far as possible this commit also merges multiple Data61 copyright statements/headers into one for consistency.
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fd83c0a3 |
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20-Mar-2019 |
Curtis Millar <curtis.millar@data61.csiro.au> |
Replace IPC_BUF_GLOBALS_FRAME with KERNEL_GLOBALS_FRAME The globals frame no longer serves its original purpose of informing a thread of its IPC buffer address, and instead as a virtual implementation of thread ID registers.
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bc5c7883 |
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19-Feb-2019 |
Yanyan Shen <yanyan.shen@data61.csiro.au> |
arm: Make Arm VCPU states per-node.
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60e2acdb |
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22-Oct-2017 |
Yanyan Shen <yanyan.shen@data61.csiro.au> |
arm/hyp: add support for running multiple ARM VMs This commit saves/restores various control registers that can be modified by guest VM kernels, so seL4 can execute multiple ARM 32-bit VMs multiplexing a single physical core. When the CONFIG_HAVE_FPU option is selected, the commit allows the VMs to use FPU registers and enables lazily saving/restoring FPU registers for the VMs.
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712efa63 |
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21-Feb-2017 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
arm_hyp: Use an explicitly invalid PD when there is no user one When the user has no PD in order to schedule them we must still set something as the active PD, just so that they can then fault. Previously when hypervisor was enabled `0` was at as the PD. This worked as platforms typically do not have anything valid, and certainly nothing resembling a page directory, at physical address 0. This assumption is not very clean and unknown physical addresses should not be accessed, so this change adds an explicit PD that is empty that can be switched to.
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48d17e1f |
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16-Jan-2017 |
Hesham Almatary <hesham.almatary@data61.csiro.au> |
ARM/SMP: Prepare for ARM SMP adding stubs Currently building ARM/SMP is broken. This commit: 1- Makes it possible to build ARM/SMP with stubs. Run-time SMP for ARM DOES NOT WORK. 2- Can be a reference for future SMP targets to follow in order to layout/add the minimal required files and functions needed to support SMP. 3- Builds for Sabre only. In order to support other platforms, ipi interrupt ID should be defined in machine.h
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53c6b524 |
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12-Jan-2017 |
Hesham Almatary <hesham.almatary@data61.csiro.au> |
SMP: Abstract architecture/platform independent parts of smp.h and ipi.h This commit is a re-arrangement of SMP directory structure to make it easier for other architectures/platforms (in general) and ARM (in particular) to add SMP support. * new include/smp directory to act as a centralised container of "shared" architecture-independent SMP headers. This makes it clearer what's needed for other architecture/platform to support SMP. * Each platform can define its own unique ipi.[h|c] that make sense, since ipi implementation is SoC/platform dependent.
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e78cdf9b |
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27-Jul-2016 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
SELFOUR-553: Support alternate IPC buffer locations without globals frame This commit adds support for using the ThreadID registers of the ARM MPCore platforms for storing the address of the IPC buffer instead of the globals frame. The choice of using the user readable/writeable ThreadID register is chosen, even though it means the user cannot use it for its own purposes, as it leaves room in the future for doing TLS support in the user read only register, where compilers expect it.
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2a1d1e94 |
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13-Oct-2016 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
arm_hyp: Add lazy vcpu switching
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04612f16 |
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13-Oct-2016 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
arm_hyp: Declare armHSCurVCPU in header
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fdad5085 |
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13-Oct-2016 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
arm_hyp: Move hype state into correct statedata header The hypervisor state is declared in arch/32/statedata.c, but is defined in arch/statedata.h. This commit moves the definitions to arch/32/statedata.h to match all the other state in arch/32/statedata.c
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2cbc7123 |
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28-Sep-2016 |
amrzar <azarrabi@nicta.com.au> |
SELFOUR-630:preliminary booting application processors - update core detection code and Kconfig file - update kernel stack managment so that BSP does not use boot stack before IPI APs - move arch dependant data to a single structure - add cache line size to Kconfig - add cpu indexing and apic id mapping - boot APs to halting state - add guard for kernel stack if there is only one core
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35c50cfd |
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29-Aug-2016 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
SELFOUR-556: Rationalize BITS vs INDEX_BITS s/PD_BITS/PD_INDEX_BITS Current convention is to say that X_BITS is the log base 2 size of an object, not the log base 2 number of indices
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f251953f |
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29-Aug-2016 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
SELFOUR-556: Rationalize BITS vs INDEX_BITS s/PT_BITS/PT_INDEX_BITS Current convention is to say that X_BITS is the log base 2 size of an object, not the log base 2 number of indices
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16c34811 |
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31-Jul-2016 |
Hesham Almatary <hesham.almatary@data61.csiro.au> |
SELFOUR-518: User-level log buffer Remove global ksLog and use KS_LOG_PPTR instead Benchmark - Log buffer: use global page table
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3fc76c25 |
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15-Jan-2016 |
amrzar <azarrabi@nicta.com.au> |
Rearranging headers for aarch32 to 32/mode/*
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