Make kernel log buffer derived from cmake config

This removes the explicit CMake configuration for the kernel log buffer
and replaces it with a #define that is enabled for the required
configurations.

Signed-off-by: Curtis Millar <curtis@curtism.me>

SMMU: TLB coherency between MMU and SMMU

The kernel connects ASID used in MMU and context banks used in
SMMU, and conducts TLB invalidation on context banks if a page
entry is invalidated from MMU is also used in SMMU.

Signed-off-by: Oliver Scott <Oliver.Scott@data61.csiro.au>

SMMU: providing master control caps to root task

Adding the master control caps that are used to create transaction
and context banks caps. This commit includes the internal kernel
structure that required to manage any created transaction and
context bank caps.

Signed-off-by: Oliver Scott <Oliver.Scott@data61.csiro.au>

Convert license tags to SPDX identifiers

This commit also converts our own copyright headers to directly use
SPDX, but leaves all other copyright header intact, only adding the
SPDX ident. As far as possible this commit also merges multiple
Data61 copyright statements/headers into one for consistency.

aarch64: add support for 40-bit PA

This commit adds support for using a 40-bit physical addresses in
aarch64-hyp mode.

40-bit PA support is implemented by using a 3-stage translation, with a
13 bit page upper directory as the vspace root. PageGlobalDirectories
are not used in this configuration.

To use 40-bit PAs, platforms should set KernelArmPASizeBits40 to ON.

Co-authored-by: Yanyan Shen <yanyan.shen@data61.csiro.au>
Co-authored-by: Chris Guikema <chris.guikema@dornerworks.com>

aarch64: abstract vspace_root in vspace code

On aarch64-hyp the virtual address translation structure can differ
depending on the physical address range. This commit prepares to support
more than a single physical address range by removing the assumption
that the top-level structure in a vspace is a PGD, replacing it with the
concept of a vspace_root.

Specifically:
- add and use macros to refer to vtable bitfield generator functions
- use the existing vspace_root_t type rather than pgde_t
- pull performASIDPoolInvocation into header
- add and use VSPACE_PTR rather than PGDE_PTR
- rename decodeARMVPageGlobalDirectoryInvocation to refer to VSpace
- update comments/error messages
- rename variables

AArch64: Modify kernel higher half mapping: increase from 510 to 512 GiB

The previous 510GiB mapping was chosen to make it easier to eyeball addresses
while debugging: it was trivial to determine the physical address that a virtual
address pertained to in the kernel with this mapping.

This was no longer considered to be a necessary benefit, so this is being
changed.

arm: Make Arm VCPU states per-node.

AArch64 Benchmark Log buffer: Astyle formatting

AArch64: Benchmark log: Add convenience pointer to PD entry

* Also document the reason why the particular address for KS_LOG_PPTR was chosen.

This patch adds a pointer to the PD entry that sets the benchmark log frame.

AArch64: Comment HYP and EL1 vaddrspace layouts

Also document the specific addresses for TX1 and TX2.

armv8/hyp: Add HW ASID variables

armv8/hyp: Add armHSCurVCPU and armHSVCPUActive

Share linker.h between architectures

Fix licenses (the rest)

s/D61/DATA61/ in license headers for consistency

aarch64: Initial implementation

aarch64: add preliminary folders and Makefiles