Searched refs:port (Results 1 - 25 of 53) sorted by relevance

123

/seL4-refos-master/kernel/include/plat/pc99/plat/machine/
H A Dio.h14 void out8(uint16_t port, uint8_t value);
16 void out16(uint16_t port, uint16_t value);
18 void out32(uint16_t port, uint32_t value);
20 uint8_t in8(uint16_t port);
22 uint16_t in16(uint16_t port);
24 uint32_t in32(uint16_t port);
27 void serial_init(uint16_t port);
/seL4-refos-master/libs/libplatsupport/src/plat/exynos5/
H A Dmux.c18 { .port = GPB3, .pin = 1, .value = MUXVALUE_CPD(2, PUD_PULLUP, DRV1X)},
19 { .port = GPB3, .pin = 0, .value = MUXVALUE_CPD(2, PUD_PULLUP, DRV1X)},
20 { .port = GPIOPORT_NONE }
23 { .port = GPB3, .pin = 3, .value = MUXVALUE_CPD(2, PUD_PULLUP, DRV1X)},
24 { .port = GPB3, .pin = 2, .value = MUXVALUE_CPD(2, PUD_PULLUP, DRV1X)},
25 { .port = GPIOPORT_NONE }
28 { .port = GPA0, .pin = 7, .value = MUXVALUE_CPD(3, PUD_PULLUP, DRV1X)},
29 { .port = GPA0, .pin = 6, .value = MUXVALUE_CPD(3, PUD_PULLUP, DRV1X)},
30 { .port = GPIOPORT_NONE }
33 { .port
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/seL4-refos-master/projects/util_libs/libplatsupport/src/plat/exynos5/
H A Dmux.c18 { .port = GPB3, .pin = 1, .value = MUXVALUE_CPD(2, PUD_PULLUP, DRV1X)},
19 { .port = GPB3, .pin = 0, .value = MUXVALUE_CPD(2, PUD_PULLUP, DRV1X)},
20 { .port = GPIOPORT_NONE }
23 { .port = GPB3, .pin = 3, .value = MUXVALUE_CPD(2, PUD_PULLUP, DRV1X)},
24 { .port = GPB3, .pin = 2, .value = MUXVALUE_CPD(2, PUD_PULLUP, DRV1X)},
25 { .port = GPIOPORT_NONE }
28 { .port = GPA0, .pin = 7, .value = MUXVALUE_CPD(3, PUD_PULLUP, DRV1X)},
29 { .port = GPA0, .pin = 6, .value = MUXVALUE_CPD(3, PUD_PULLUP, DRV1X)},
30 { .port = GPIOPORT_NONE }
33 { .port
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/seL4-refos-master/kernel/src/plat/pc99/machine/
H A Dio.c14 void serial_init(uint16_t port) argument
16 while (!(in8(port + 5) & 0x60)); /* wait until not busy */
18 out8(port + 1, 0x00); /* disable generating interrupts */
19 out8(port + 3, 0x80); /* line control register: command: set divisor */
20 out8(port, 0x01); /* set low byte of divisor to 0x01 = 115200 baud */
21 out8(port + 1, 0x00); /* set high byte of divisor to 0x00 */
22 out8(port + 3, 0x03); /* line control register: set 8 bit, no parity, 1 stop bit */
23 out8(port + 4, 0x0b); /* modem control register: set DTR/RTS/OUT2 */
25 in8(port); /* clear receiver port */
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/seL4-refos-master/libs/libplatsupport/src/plat/exynos4/
H A Dmux.c17 { .port = GPD1, .pin = 0, MUXVALUE_CPD(2, PUD_PULLUP, DRV1X)},
18 { .port = GPD1, .pin = 1, MUXVALUE_CPD(2, PUD_PULLUP, DRV1X)},
19 { .port = GPIOPORT_NONE }
22 { .port = GPD1, .pin = 2, MUXVALUE_CPD(2, PUD_PULLUP, DRV1X)},
23 { .port = GPD1, .pin = 3, MUXVALUE_CPD(2, PUD_PULLUP, DRV1X)},
24 { .port = GPIOPORT_NONE }
28 { .port = GPA0, .pin = 6, MUXVALUE_CPD(3, PUD_PULLUP, DRV1X)},
29 { .port = GPA0, .pin = 7, MUXVALUE_CPD(3, PUD_PULLUP, DRV1X)},
30 { .port = GPIOPORT_NONE }
34 { .port
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/seL4-refos-master/projects/util_libs/libplatsupport/src/plat/exynos4/
H A Dmux.c17 { .port = GPD1, .pin = 0, MUXVALUE_CPD(2, PUD_PULLUP, DRV1X)},
18 { .port = GPD1, .pin = 1, MUXVALUE_CPD(2, PUD_PULLUP, DRV1X)},
19 { .port = GPIOPORT_NONE }
22 { .port = GPD1, .pin = 2, MUXVALUE_CPD(2, PUD_PULLUP, DRV1X)},
23 { .port = GPD1, .pin = 3, MUXVALUE_CPD(2, PUD_PULLUP, DRV1X)},
24 { .port = GPIOPORT_NONE }
28 { .port = GPA0, .pin = 6, MUXVALUE_CPD(3, PUD_PULLUP, DRV1X)},
29 { .port = GPA0, .pin = 7, MUXVALUE_CPD(3, PUD_PULLUP, DRV1X)},
30 { .port = GPIOPORT_NONE }
34 { .port
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/seL4-refos-master/libs/libmuslc/src/network/
H A Dgetservbyport.c4 struct servent *getservbyport(int port, const char *prots) argument
9 if (getservbyport_r(port, prots, &se, (void *)buf, sizeof buf, &res))
H A Dlookup_serv.c16 unsigned long port = 0; local
42 buf[0].port = 0;
50 port = strtoul(name, &z, 10);
53 if (port > 65535) return EAI_SERVICE;
55 buf[cnt].port = port;
60 buf[cnt].port = port;
96 port = strtoul(p, &z, 10);
97 if (port > 6553
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H A Dgetservbyport_r.c9 int getservbyport_r(int port, const char *prots, argument
15 .sin_port = port,
19 int r = getservbyport_r(port, "tcp", se, buf, buflen, res);
20 if (r) r = getservbyport_r(port, "udp", se, buf, buflen, res);
35 se->s_port = port;
H A Dlookup.h15 uint16_t port; member in struct:service
/seL4-refos-master/projects/util_libs/libethdrivers/src/plat/imx6/uboot/
H A Dmxc_gpio.c45 /* GPIO port description */
89 unsigned int port = GPIO_TO_PORT(gpio); local
93 if (port >= ARRAY_SIZE(gpio_ports)) {
99 if (gpio_ports[port] == 0) {
100 uintptr_t gpio_phys = (uintptr_t)gpio_paddr[port];
101 gpio_ports[port] = (unsigned long)ps_io_map(&io_ops->io_mapper, gpio_phys, GPIO_SIZE, 0, PS_MEM_NORMAL);
102 if (gpio_ports[port] == 0) {
103 LOG_ERROR("Warning: No map for GPIO %d. Assuming that it is already configured\n", port);
108 regs = (struct gpio_regs *)gpio_ports[port];
125 unsigned int port local
150 unsigned int port = GPIO_TO_PORT(gpio); local
169 unsigned int port = GPIO_TO_PORT(gpio); local
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H A Dgpio.h68 #define IMX_GPIO_NR(port, index) ((((port)-1)*32)+((index)&31))
/seL4-refos-master/libs/libsel4platsupport/src/arch/x86/
H A Dio_port_ops.c28 sel4platsupport_io_port_in(void *cookie, uint32_t port, int io_size, uint32_t *result) argument
31 uint32_t last_port = port + io_size - 1;
39 error = simple_get_IOPort_cap(io_cookie->simple, port, last_port, path.root, path.capPtr, path.capDepth);
41 ZF_LOGE("Failed to get capability for IOPort range 0x%x-0x%x", port, last_port);
47 seL4_X86_IOPort_In8_t x = seL4_X86_IOPort_In8(path.capPtr, port);
53 seL4_X86_IOPort_In16_t x = seL4_X86_IOPort_In16(path.capPtr, port);
59 seL4_X86_IOPort_In32_t x = seL4_X86_IOPort_In32(path.capPtr, port);
76 sel4platsupport_io_port_out(void *cookie, uint32_t port, int io_size, uint32_t val) argument
79 uint32_t last_port = port + io_size - 1;
87 error = simple_get_IOPort_cap(io_cookie->simple, port, last_por
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/seL4-refos-master/projects/seL4_libs/libsel4platsupport/src/arch/x86/
H A Dio_port_ops.c28 sel4platsupport_io_port_in(void *cookie, uint32_t port, int io_size, uint32_t *result) argument
31 uint32_t last_port = port + io_size - 1;
39 error = simple_get_IOPort_cap(io_cookie->simple, port, last_port, path.root, path.capPtr, path.capDepth);
41 ZF_LOGE("Failed to get capability for IOPort range 0x%x-0x%x", port, last_port);
47 seL4_X86_IOPort_In8_t x = seL4_X86_IOPort_In8(path.capPtr, port);
53 seL4_X86_IOPort_In16_t x = seL4_X86_IOPort_In16(path.capPtr, port);
59 seL4_X86_IOPort_In32_t x = seL4_X86_IOPort_In32(path.capPtr, port);
76 sel4platsupport_io_port_out(void *cookie, uint32_t port, int io_size, uint32_t val) argument
79 uint32_t last_port = port + io_size - 1;
87 error = simple_get_IOPort_cap(io_cookie->simple, port, last_por
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/seL4-refos-master/projects/util_libs/libethdrivers/src/plat/am335x/cpsw/
H A Dcpswif.c5 * lwIP Ethernet interface for CPSW port
186 cpswinst->port[PORT_1].port_base = eth_data->iomm_address.eth_mmio_cpsw_reg + 0x200;
187 cpswinst->port[PORT_1].sliver_base = eth_data->iomm_address.eth_mmio_cpsw_reg + 0xD80;
188 cpswinst->port[PORT_2].port_base = eth_data->iomm_address.eth_mmio_cpsw_reg + 0x300;
189 cpswinst->port[PORT_2].sliver_base = eth_data->iomm_address.eth_mmio_cpsw_reg + 0xDC0;
222 * @param port_num The slave port number
253 * @param portmask The port mask for the port number
284 * @param port_num The slave port number
304 & (1 << cpswinst->port[port_nu
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H A Dcpswif.h101 #define CPDMA_BUF_DESC_TO_PORT(port) ((port << 16) | 0x100000)
152 * Slave port information
171 /* CPSW port number */
190 /* Slave port information */
191 struct cpswport port[MAX_SLAVEPORT_PER_INST]; member in struct:cpswinst
/seL4-refos-master/kernel/src/arch/x86/object/
H A Dioport.c141 userError("IOPortControl: Last port must be > first port.");
170 static exception_t invokeX86PortIn(word_t invLabel, uint16_t port, bool_t call) argument
177 res = in8(port);
180 res = in16(port);
183 res = in32(port);
216 static exception_t invokeX86PortOut(word_t invLabel, uint16_t port, uint32_t data) argument
220 out8(port, data);
223 out16(port, data);
226 out32(port, dat
253 uint16_t port = getSyscallArg(0, buffer) & 0xffff; local
278 uint16_t port = getSyscallArg(0, buffer) & 0xffff; local
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/seL4-refos-master/libs/libplatsupport/plat_include/exynos4/platsupport/plat/
H A Dgpio.h19 #define _GPIOPORT(bank, port) (((bank) << 8) | (port))
20 #define GPIOPORT_GET_BANK(port) ((port) >> 8)
21 #define GPIOPORT_GET_PORT(port) ((port) & 0xff)
22 #define GPIOPORT(bank, port) _GPIOPORT(GPIO_##bank##_BANK, port)
/seL4-refos-master/libs/libplatsupport/plat_include/exynos5/platsupport/plat/
H A Dgpio.h18 #define _GPIOPORT(bank, port) (((bank) << 8) | (port))
19 #define GPIOPORT_GET_BANK(port) ((port) >> 8)
20 #define GPIOPORT_GET_PORT(port) ((port) & 0xff)
21 #define GPIOPORT(bank, port) _GPIOPORT(GPIO_##bank##_BANK, port)
/seL4-refos-master/projects/util_libs/libplatsupport/plat_include/exynos4/platsupport/plat/
H A Dgpio.h19 #define _GPIOPORT(bank, port) (((bank) << 8) | (port))
20 #define GPIOPORT_GET_BANK(port) ((port) >> 8)
21 #define GPIOPORT_GET_PORT(port) ((port) & 0xff)
22 #define GPIOPORT(bank, port) _GPIOPORT(GPIO_##bank##_BANK, port)
/seL4-refos-master/projects/util_libs/libplatsupport/plat_include/exynos5/platsupport/plat/
H A Dgpio.h18 #define _GPIOPORT(bank, port) (((bank) << 8) | (port))
19 #define GPIOPORT_GET_BANK(port) ((port) >> 8)
20 #define GPIOPORT_GET_PORT(port) ((port) & 0xff)
21 #define GPIOPORT(bank, port) _GPIOPORT(GPIO_##bank##_BANK, port)
/seL4-refos-master/projects/util_libs/libplatsupport/src/mach/exynos/
H A Dmux.c45 static struct mux_cfg *get_mux_cfg(const mux_sys_t *mux, int port) argument
50 b = GPIOPORT_GET_BANK(port);
51 p = GPIOPORT_GET_PORT(port);
152 for (; data->port != GPIOPORT_NONE; data++) {
155 ZF_LOGD("Enabling feature: bank %d, port %d, pin %d\n",
156 GPIOPORT_GET_BANK(data->port),
157 GPIOPORT_GET_PORT(data->port),
160 cfg = get_mux_cfg(mux, data->port);
261 int portid, port; local
263 port
270 int portid, port; local
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/seL4-refos-master/libs/libplatsupport/src/mach/exynos/
H A Dmux.c45 static struct mux_cfg *get_mux_cfg(const mux_sys_t *mux, int port) argument
50 b = GPIOPORT_GET_BANK(port);
51 p = GPIOPORT_GET_PORT(port);
152 for (; data->port != GPIOPORT_NONE; data++) {
155 ZF_LOGD("Enabling feature: bank %d, port %d, pin %d\n",
156 GPIOPORT_GET_BANK(data->port),
157 GPIOPORT_GET_PORT(data->port),
160 cfg = get_mux_cfg(mux, data->port);
261 int portid, port; local
263 port
270 int portid, port; local
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/seL4-refos-master/libs/librefos/src/refos-util/
H A Ddevice_io.c27 unmapping, DMA allocation, and x86 IO port operations.
119 dev_io_port_in(void* cookie, uint32_t port, int io_size, uint32_t *result) argument
137 res8 = seL4_X86_IOPort_In8(io->IOPorts, port);
143 res16 = seL4_X86_IOPort_In16(io->IOPorts, port);
149 res32 = seL4_X86_IOPort_In32(io->IOPorts, port);
162 dev_io_port_out(void* cookie, uint32_t port, int io_size, uint32_t val) argument
172 seL4_X86_IOPort_Out8(io->IOPorts, port, (uint8_t) val);
175 seL4_X86_IOPort_Out16(io->IOPorts, port, (uint16_t) val);
178 seL4_X86_IOPort_Out32(io->IOPorts, port, (uint32_t) val);
240 /* Set the function pointers for the IO port operation
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/seL4-refos-master/projects/refos/impl/libs/librefos/src/refos-util/
H A Ddevice_io.c27 unmapping, DMA allocation, and x86 IO port operations.
119 dev_io_port_in(void* cookie, uint32_t port, int io_size, uint32_t *result) argument
137 res8 = seL4_X86_IOPort_In8(io->IOPorts, port);
143 res16 = seL4_X86_IOPort_In16(io->IOPorts, port);
149 res32 = seL4_X86_IOPort_In32(io->IOPorts, port);
162 dev_io_port_out(void* cookie, uint32_t port, int io_size, uint32_t val) argument
172 seL4_X86_IOPort_Out8(io->IOPorts, port, (uint8_t) val);
175 seL4_X86_IOPort_Out16(io->IOPorts, port, (uint16_t) val);
178 seL4_X86_IOPort_Out32(io->IOPorts, port, (uint32_t) val);
240 /* Set the function pointers for the IO port operation
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