1/* @TAG(CUSTOM) */
2
3/**
4 * @file - cpswif.h
5 * Prototypes for CPSW Ethernet interface.
6 *
7 */
8
9/*
10 * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
11 * All rights reserved.
12 *
13 * Redistribution and use in source and binary forms, with or without modification,
14 * are permitted provided that the following conditions are met:
15 *
16 * 1. Redistributions of source code must retain the above copyright notice,
17 *    this list of conditions and the following disclaimer.
18 * 2. Redistributions in binary form must reproduce the above copyright notice,
19 *    this list of conditions and the following disclaimer in the documentation
20 *    and/or other materials provided with the distribution.
21 * 3. The name of the author may not be used to endorse or promote products
22 *    derived from this software without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
25 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
26 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
27 * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
28 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
29 * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
32 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
33 * OF SUCH DAMAGE.
34 *
35 * This file is part of the lwIP TCP/IP stack.
36 *
37 * Author: Adam Dunkels <adam@sics.se>
38 *
39 */
40
41/*
42 * Copyright (c) 2010 Texas Instruments Incorporated
43 *
44 */
45#include <lwip/netif.h>
46#include <platsupport/io.h>
47#include <ethdrivers/raw.h>
48
49#ifndef __CPSWIF_H__
50#define __CPSWIF_H__
51
52/***************************************************************************/
53/*
54 * Configurations for AM335x
55 */
56#ifdef CONFIG_PLAT_AM335X
57#include <ethdrivers/plat/hw/soc_AM335x.h>
58
59#define MAX_CPSW_INST                   1
60#define CPSW0_SS_REGS                   SOC_CPSW_SS_REGS
61#define CPSW0_MDIO_REGS                 SOC_CPSW_MDIO_REGS
62#define CPSW0_WR_REGS                   SOC_CPSW_WR_REGS
63#define CPSW0_CPDMA_REGS                SOC_CPSW_CPDMA_REGS
64#define CPSW0_ALE_REGS                  SOC_CPSW_ALE_REGS
65#define CPSW0_CPPI_RAM_REGS             SOC_CPSW_CPPI_RAM_REGS
66#define CPSW0_PORT_0_REGS               SOC_CPSW_PORT_0_REGS
67#define CPSW0_PORT_1_REGS               SOC_CPSW_PORT_1_REGS
68#define CPSW0_SLIVER_1_REGS             SOC_CPSW_SLIVER_1_REGS
69#define CPSW0_PORT_2_REGS               SOC_CPSW_PORT_2_REGS
70#define CPSW0_SLIVER_2_REGS             SOC_CPSW_SLIVER_2_REGS
71
72/* CPPI RAM size in bytes */
73#ifndef SIZE_CPPI_RAM
74#define SIZE_CPPI_RAM                            0x2000
75#endif
76
77#define PORT_1                                   0x0
78#define PORT_2                                   0x1
79#define PORT_0_MASK                              0x1
80#define PORT_1_MASK                              0x2
81#define PORT_2_MASK                              0x4
82#define HOST_PORT_MASK                           PORT_0_MASK
83#define SLAVE_PORT_MASK(slv_port_num)            (1 << slv_port_num)
84#define PORT_MASK                                (0x7)
85#define INDV_PORT_MASK(slv_port_num)             (1 << slv_port_num)
86
87#define ENTRY_TYPE                               0x30
88#define ENTRY_TYPE_IDX                           7
89#define ENTRY_FREE                               0
90
91/* MDIO input and output frequencies in Hz */
92#define MDIO_FREQ_INPUT                          125000000
93#define MDIO_FREQ_OUTPUT                         1000000
94
95#define CPDMA_BUF_DESC_OWNER                     0x20000000
96#define CPDMA_BUF_DESC_SOP                       0x80000000
97#define CPDMA_BUF_DESC_EOP                       0x40000000
98#define CPDMA_BUF_DESC_EOQ                       0x10000000
99#define CPDMA_BUF_DESC_FROM_PORT                 0x70000
100#define CPDMA_BUF_DESC_FROM_PORT_SHIFT           16
101#define CPDMA_BUF_DESC_TO_PORT(port)             ((port << 16) | 0x100000)
102#define CPDMA_BD_LEN_MASK                        0xFFFF
103#define CPDMA_BD_PKTLEN_MASK                     0xFFFF
104
105#define MAX_TRANSFER_UNIT                        1500
106#define PBUF_LEN_MAX                             1520
107
108#define MIN_PKT_LEN                              60
109
110#ifndef FALSE
111# define FALSE 0
112#endif
113#ifndef TRUE
114# define TRUE 1
115#endif
116
117#ifdef evmAM335x
118#define CPSW0_PORT_1_PHY_ADDR           0
119#define CPSW0_PORT_1_PHY_GIGABIT        TRUE
120
121#elif defined(beaglebone)
122#define CPSW0_PORT_1_PHY_ADDR           0
123#define CPSW0_PORT_1_PHY_GIGABIT        FALSE
124
125#elif defined(evmskAM335x)
126#define CPSW0_PORT_1_PHY_ADDR           0
127#define CPSW0_PORT_2_PHY_ADDR           1
128#define CPSW0_PORT_1_PHY_GIGABIT        TRUE
129#define CPSW0_PORT_2_PHY_GIGABIT        TRUE
130#endif
131
132#define LWIP_PRINTF                     printf
133
134#else
135#error Unsupported EVM !!!
136#endif
137
138#define MAX_SLAVEPORT_PER_INST          2
139
140#define SIZE_CPPI_RAM                            0x2000
141
142#define VPTR_CPSW_CPPI(cpsw_base) ((cpsw_base) + 0x2000)
143#define VPTR_CPSW_CPDMA(cpsw_base) ((cpsw_base) + 0x800)
144
145struct EthVirtAddr {
146    uintptr_t eth_mmio_ctr_reg;
147    uintptr_t eth_mmio_prcm_reg;
148    uintptr_t eth_mmio_cpsw_reg;
149};
150
151/**
152 * Slave port information
153 */
154struct cpswport {
155    u32_t port_base;
156    u32_t sliver_base;
157    u32_t phy_addr;
158
159    /* The PHY is capable of GitaBit or Not */
160    u32_t phy_gbps;
161} cpswport;
162
163/*****************************************************************************/
164/**
165 * Helper struct to hold private data used to operate the ethernet interface.
166 */
167struct cpswportif {
168    /* CPSW instance number */
169    u32_t inst_num;
170
171    /* CPSW port number */
172    u32_t port_num;
173
174    u8_t eth_addr[6];
175} cpswportif;
176
177/**
178 * CPSW instance information
179 */
180struct cpswinst {
181    /* Base addresses */
182    u32_t ss_base;
183    u32_t mdio_base;
184    u32_t wrpr_base;
185    u32_t ale_base;
186    u32_t cpdma_base;
187    u32_t cppi_ram_base;
188    u32_t host_port_base;
189
190    /* Slave port information */
191    struct cpswport port[MAX_SLAVEPORT_PER_INST];
192} cpswinst;
193
194/* TX and RX Buffer descriptor data structure (used by the device) */
195struct descriptor {
196    uintptr_t next;
197    volatile uint32_t bufptr;
198    volatile uint32_t bufoff_len;
199    volatile uint32_t flags_pktlen;
200};
201
202struct beaglebone_eth_data {
203    struct cpswportif *cpswPortIf;
204    struct cpswinst   *cpswinst;
205    uintptr_t tx_ring_phys;
206    uintptr_t rx_ring_phys;
207    volatile struct descriptor *tx_ring;
208    volatile struct descriptor *rx_ring;
209    unsigned int rx_size;
210    unsigned int tx_size;
211    void **rx_cookies;
212    unsigned int rx_remain;
213    unsigned int tx_remain;
214    void **tx_cookies;
215    unsigned int *tx_lengths;
216    /* track where the head and tail of the queues are for
217     * enqueueing buffers / checking for completions */
218    unsigned int rdt, rdh, tdt, tdh;
219    struct EthVirtAddr iomm_address;
220};
221
222extern u32_t cpswif_netif_status(struct netif *netif);
223extern u32_t cpswif_link_status(struct eth_driver *driver, u32_t inst_num, u32_t slv_port_num);
224extern err_t cpswif_init(struct eth_driver *driver);
225
226#endif /* _CPSWIF_H__ */
227