Searched refs:seL4_LargePageBits (Results 1 - 22 of 22) sorted by relevance

/seL4-l4v-10.1.1/seL4/include/plat/pc99/plat/32/plat_mode/machine/
H A Dhardware.h22 #define PPTR_USER_TOP (PPTR_BASE & (~MASK(seL4_LargePageBits)))
26 #define TLBBITMAP_PD_RESERVED (TLBBITMAP_ROOT_ENTRIES * BIT(seL4_LargePageBits))
30 #define LOGBUFFER_PD_RESERVED BIT(seL4_LargePageBits)
/seL4-l4v-10.1.1/seL4/include/arch/x86/arch/machine/
H A Dhardware.h21 #define LARGE_PAGE_BITS seL4_LargePageBits
41 X64LargePageBits = seL4_LargePageBits,
67 return seL4_LargePageBits;
90 return seL4_LargePageBits;
/seL4-l4v-10.1.1/seL4/include/arch/riscv/arch/32/mode/api/
H A Dconstants.h45 #define seL4_LargePageBits 22 macro
/seL4-l4v-10.1.1/seL4/include/arch/riscv/arch/64/mode/api/
H A Dconstants.h41 #define seL4_LargePageBits 21 macro
/seL4-l4v-10.1.1/seL4/libsel4/sel4_arch_include/riscv32/sel4/sel4_arch/
H A Dconstants.h45 #define seL4_LargePageBits 22 macro
/seL4-l4v-10.1.1/seL4/libsel4/sel4_arch_include/riscv64/sel4/sel4_arch/
H A Dconstants.h41 #define seL4_LargePageBits 21 macro
/seL4-l4v-10.1.1/seL4/include/arch/x86/arch/32/mode/api/
H A Dconstants.h50 #define seL4_LargePageBits 22 /* 4MB */ macro
60 #define seL4_4MBits seL4_LargePageBits
/seL4-l4v-10.1.1/seL4/libsel4/sel4_arch_include/ia32/sel4/sel4_arch/
H A Dconstants.h50 #define seL4_LargePageBits 22 /* 4MB */ macro
60 #define seL4_4MBits seL4_LargePageBits
/seL4-l4v-10.1.1/seL4/src/arch/x86/32/kernel/
H A Dvspace_32paging.c74 for (i = 0; i < (PPTR_BASE >> seL4_LargePageBits); i++) {
76 i << seL4_LargePageBits, /* physical address */
91 for (i = 0; i < ((-PPTR_BASE) >> seL4_LargePageBits); i++) {
92 *(_boot_pd + i + (PPTR_BASE >> seL4_LargePageBits)) = pde_pde_large_new_phys(
93 (i << seL4_LargePageBits) + PADDR_BASE, /* physical address */
116 *(pd + (vptr >> seL4_LargePageBits)) = pde_pde_pt_new(
145 pd += (vptr >> seL4_LargePageBits);
147 *(pt + ((vptr & MASK(seL4_LargePageBits)) >> seL4_PageBits)) = pte_new(
201 for (i = PPTR_BASE >> seL4_LargePageBits; i < BIT(PD_INDEX_BITS); i++) {
342 offset = vaddr & MASK(seL4_LargePageBits);
[all...]
/seL4-l4v-10.1.1/seL4/include/arch/arm/arch/64/mode/machine/
H A Dhardware.h58 ARMLargePageBits = seL4_LargePageBits,
/seL4-l4v-10.1.1/seL4/include/arch/riscv/arch/machine/
H A Dhardware.h66 RISCVMegaPageBits = seL4_LargePageBits,
/seL4-l4v-10.1.1/seL4/include/arch/x86/arch/64/mode/api/
H A Dconstants.h57 #define seL4_LargePageBits 21 macro
/seL4-l4v-10.1.1/seL4/libsel4/sel4_arch_include/x86_64/sel4/sel4_arch/
H A Dconstants.h57 #define seL4_LargePageBits 21 macro
/seL4-l4v-10.1.1/seL4/include/arch/arm/arch/32/mode/api/
H A Dconstants.h132 #define seL4_LargePageBits 16 macro
/seL4-l4v-10.1.1/seL4/include/arch/arm/arch/32/mode/machine/
H A Dhardware.h140 ARMLargePageBits = seL4_LargePageBits,
/seL4-l4v-10.1.1/seL4/include/arch/arm/arch/64/mode/api/
H A Dconstants.h123 #define seL4_LargePageBits 21 macro
/seL4-l4v-10.1.1/seL4/libsel4/sel4_arch_include/aarch32/sel4/sel4_arch/
H A Dconstants.h132 #define seL4_LargePageBits 16 macro
/seL4-l4v-10.1.1/seL4/libsel4/sel4_arch_include/aarch64/sel4/sel4_arch/
H A Dconstants.h123 #define seL4_LargePageBits 21 macro
/seL4-l4v-10.1.1/seL4/libsel4/sel4_arch_include/arm_hyp/sel4/sel4_arch/
H A Dconstants.h132 #define seL4_LargePageBits 16 macro
/seL4-l4v-10.1.1/seL4/src/arch/riscv/object/
H A Dobjecttype.c192 return seL4_LargePageBits;
/seL4-l4v-10.1.1/seL4/src/arch/x86/64/kernel/
H A Dvspace.c291 assert((skim_start % BIT(seL4_LargePageBits)) == 0);
292 assert((skim_end % BIT(seL4_LargePageBits)) == 0);
308 paddr += BIT(seL4_LargePageBits);
1637 offset = vaddr & MASK(seL4_LargePageBits);
/seL4-l4v-10.1.1/seL4/src/arch/arm/64/kernel/
H A Dvspace.c275 assert(IS_ALIGNED(kernelBase, seL4_LargePageBits));
295 for (paddr = physBase; paddr < PADDR_TOP; paddr += BIT(seL4_LargePageBits)) {
309 vaddr += BIT(seL4_LargePageBits);

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