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d94eda31 |
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18-Jun-2018 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
riscv: Respect deviceMemory Passes the `deviceMemory` flag given to `Arch_createObject` into the frame cap instead of pretending that all frames are valid kernel object memory.
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ca9de60b |
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18-Jun-2018 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
riscv: Do not zero memory in Arch_createObject It use to be be the responsibility of createObject, and by extension Arch_createObject, to zero memory if so required. Since the riscv port was originally started the responsiblity of zering the memory was moved to generic untyped retype handling, however this change was never propogated to the riscv architecture. As it stands this memory zeroing is guaranteed to zero memory that was already zeroed, which is just a performance (and proof), issue and so we want to remove them.
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b4b7f194 |
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18-Jun-2018 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
riscv: Add extra device frame check This check is redundant, but provides a simplification for verification.
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f3f86874 |
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18-Jun-2018 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
riscv: Handle ASID caps in Arch_sameRegionAs
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82ba5150 |
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18-Jun-2018 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
riscv: Handle ASID caps in Arch_finaliseCap
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f8f5efc7 |
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18-Jun-2018 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
riscv: Mask frame cap rights Correctly updates cap rights for new cap permissions through an updateCapData call
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1b68590b |
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11-Apr-2018 |
Anna Lyons <Anna.Lyons@data61.csiro.au> |
riscv: use one definition of page bits
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f0bd4437 |
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09-Apr-2018 |
Anna Lyons <Anna.Lyons@data61.csiro.au> |
riscv: check all frame types in Arch_isFrameType
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8ccfef60 |
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05-Apr-2018 |
Anna Lyons <Anna.Lyons@data61.csiro.au> |
riscv: finally remove isVTableRoot with last usage Where and how we use this is context dependent so it is now inlined
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23d83d6c |
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04-Apr-2018 |
Anna Lyons <Anna.Lyons@data61.csiro.au> |
riscv: remove capFTMapType it is not used on riscv
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635a6da4 |
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03-Apr-2018 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
riscv: Remove incorrectly formatted printf
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ae5df972 |
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03-Apr-2018 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
riscv: Simplify Arch_decodeInvocation riscv only has a single kind of arch invocation, that for MMUs.
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b9bf2c05 |
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03-Apr-2018 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
riscv: Remove unused function
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5b17cd96 |
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02-Apr-2018 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
riscv: Missing arch cap abstractions These are needed after rebase
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aafa5942 |
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27-Mar-2018 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
RISCV: Place TODOs in the source
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83ba0847 |
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20-Feb-2018 |
Hesham Almatary <hesham.almatary@unsw.edu.au> |
[SELFOUR-1156] RISC-V Port Experimental release that supports both RV32 and RV64
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