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7b8f6106 |
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08-May-2018 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
x86: Consistently compare against PPTR_USER_TOP PPTR_USER_TOP is the last valid user address and so any address greater than it should not be used. Due to pages being at least 4K aligned it is also correct to do a >= comparison, but it is clearer and more consistent with verification to perform just >.
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#
128829a9 |
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11-Sep-2017 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
x86: Rationalize names of paging structures Changes the name of paging structure entries to more clearly indicate the kind of object they map to. Generally this is changing a `pde_small` to `pde_pt` to indicate that this mapping refers to a page table, removing an inconsistency where `pde_large` indicated that the mapping was for a large page. For the same reason the `ept_pde_4k` type is changed to `ept_pde_pt` type to reflect what is present in the actual entry. `pde_large` is left as 'large' and not explicitly given a size as code common between ia32 and x86-64 manipulates these entities and 'large' is already a used abstraction over the two potential page sizes so there is need to introduce a formal abstraction layer and make the names in the structures more specific.
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f85fb62f |
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21-Aug-2017 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
SELFOUR-1062: Hide all VT-x related code behind #ifdef guards The VT-x implementation is not going to be verified at the moment, and so the code for it needs to be hidden from verification, which we do by #ifdef'ing it out if the VT-x is not enabled. As a result the VT-x configuration depends on a non verification target
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57fa0e0f |
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07-Aug-2017 |
Hesham Almatary <hesham.almatary@data61.csiro.au> |
Share linker.h between architectures
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958239a9 |
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13-Jun-2017 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
x86: Restructure performASIDPoolInvocation Swap the `if` cases in this function so that the default else case becomes one that always happens, with an `assert`, and the vtx case becomes guarded with a config_set This ensures that * All code paths have either a check or assertion on having a correct cap type * Compiler can see that all code paths will correctly set `asid_map` before using it
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bc380859 |
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21-May-2017 |
Bamboo <bamboo@keg.ertos.in.nicta.com.au> |
[STYLE_FIX]
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bac7826a |
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21-May-2017 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
Avoid using bitfield generated *_ptr_new functions These functions can cause slow down during verification C parsing and do not currently have any proofs about them. More importantly there is no performance impact from just calling the regular *_new functions instead
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9ca253a3 |
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07-May-2017 |
Anna Lyons <Anna.Lyons@data61.csiro.au> |
SELFOUR-879: expose index and entry constants
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3e57e647 |
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19-Oct-2016 |
Hesham Almatary <hesham.almatary@data61.csiro.au> |
SELFOUR-501: x86 - Remove PAE support
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3ba3f2de |
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04-Dec-2016 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
x86: Add BSS regions for BOOT and PHYS code Uninitialized data structures in BOOT and PHYS code currently get placed in sections that are allocated in the file of the final image. Whilst these sections will get reclaimed during kernel boot, so no runtime memory is being wasted, it results in kernel images that are much larger to load and transport than necesary. This change adds explicit BSS regions for both BOOT and PHYS code and moves all appropriate data structures into them
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d5070775 |
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10-Nov-2016 |
Anna Lyons <Anna.Lyons@data61.csiro.au> |
x86: use setMR instead of setRegister in vspace. Otherwise if the number of MRs is altered this code can break.
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056dbf81 |
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02-Nov-2016 |
amrzar <azarrabi@nicta.com.au> |
SELFOUR-634: support for TLB and cache management
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7fbde1bb |
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14-Jun-2016 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
SELFOUR-287: 32-bit vt-x implementation This is an implementation of vt-x for x86 kernels running in ia32 mode.
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3f9eb7c8 |
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06-Oct-2016 |
amrzar <azarrabi@nicta.com.au> |
SELFOUR-632: implement cores non-architecture dependent structres
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35c50cfd |
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29-Aug-2016 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
SELFOUR-556: Rationalize BITS vs INDEX_BITS s/PD_BITS/PD_INDEX_BITS Current convention is to say that X_BITS is the log base 2 size of an object, not the log base 2 number of indices
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f251953f |
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29-Aug-2016 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
SELFOUR-556: Rationalize BITS vs INDEX_BITS s/PT_BITS/PT_INDEX_BITS Current convention is to say that X_BITS is the log base 2 size of an object, not the log base 2 number of indices
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f34f354a |
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16-Aug-2016 |
Anna Lyons <Anna.Lyons@data61.csiro.au> |
SELFOUR-617: one source of memory object sizes Adds the following constants to libsel4 and uses them in the kernel. seL4_SectionSize (arm) seL4_SuperSectionSize (arm) seL4_HugePageSize (x86 - pae) seL4_LargePageSize (arm) seL4_DataFault seL4_InstructionFault
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8891f42a |
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25-May-2016 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
trivial: style
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0d73506a |
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23-May-2016 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
SELFOUR-484 x86: Get status bits invocation This adds an invocation on page directories that returns the status (accessed + dirty) bits of mapping.
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d500e333 |
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24-May-2016 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
trivial: style
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9aeee987 |
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24-May-2016 |
Adrian Danis <Adrian.Danis@data61.csiro.au> |
SELFOUR-449 Implement user stack trace on double fault
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cf6e5c8e |
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17-Nov-2015 |
Adrian Danis <Adrian.Danis@nicta.com.au> |
x86: Use typedef for vspace roots instead of void*
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d93699c9 |
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04-Jan-2016 |
Anna Lyons <Anna.Lyons@nicta.com.au> |
SELFOUR-114: remove duplication of seL4_MessageInfo_t, adjust naming to avoid cparser mangling
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4e81ed05 |
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05-Nov-2015 |
Adrian Danis <Adrian.Danis@nicta.com.au> |
x86: Extract 32-bit specific vspace functions in mode/vspace.c
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b03c6dbf |
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09-Nov-2015 |
Adrian Danis <Adrian.Danis@nicta.com.au> |
x86: With multi-kernel support removed make the kernel PDs etc global instead of passing them around
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#
ef85f94a |
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05-Nov-2015 |
Adrian Danis <Adrian.Danis@nicta.com.au> |
x86: Rename constants and functions to have X86 prefix instead of IA32 prefix
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198f6c84 |
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01-Jun-2015 |
Adrian Danis <Adrian.Danis@nicta.com.au> |
x86: Move 32-bit specific files into 'mode' directories, and only build if IA32
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