/openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/ |
H A D | dcn20_clk_mgr.c | 109 clk_mgr->dccg->ref_dppclk = clk_mgr->base.clks.dppclk_khz; 111 int dpp_inst, dppclk_khz, prev_dppclk_khz; local 117 dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz; 121 if (safe_to_lower || prev_dppclk_khz < dppclk_khz) 123 clk_mgr->dccg, dpp_inst, dppclk_khz); 136 if (clk_mgr->base.clks.dppclk_khz == 0 || clk_mgr->base.clks.dispclk_khz == 0) 140 * clk_mgr->base.dentist_vco_freq_khz / clk_mgr->base.clks.dppclk_khz; 296 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) { [all...] |
/openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn201/ |
H A D | dcn201_clk_mgr.c | 139 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) { 140 if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz) 142 clk_mgr->base.clks.dppclk_khz = new_clocks->dppclk_khz;
|
/openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/ |
H A D | rn_clk_mgr.c | 114 int dpp_inst, dppclk_khz, prev_dppclk_khz; local 120 dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz; 124 if (safe_to_lower || prev_dppclk_khz < dppclk_khz) 126 clk_mgr->dccg, dpp_inst, dppclk_khz); 187 if (new_clocks->dppclk_khz < 100000 && new_clocks->dppclk_khz > 0) 188 new_clocks->dppclk_khz = 100000; 194 if (new_clocks->dppclk_khz == 0 || new_clocks->dispclk_khz == 0) { 195 new_clocks->dppclk_khz [all...] |
/openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/ |
H A D | dcn316_clk_mgr.c | 202 if (new_clocks->dppclk_khz < 100000) 203 new_clocks->dppclk_khz = 100000; 207 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) { 208 if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz) 210 clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz; 227 dcn316_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz); 231 dcn316_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz); [all...] |
/openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/ |
H A D | dcn32_clk_mgr.c | 281 if (new_clocks->dppclk_khz) { 283 * clk_mgr->base.dentist_vco_freq_khz / new_clocks->dppclk_khz; 284 new_clocks->dppclk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR * clk_mgr->base.dentist_vco_freq_khz) / dpp_divider; 298 clk_mgr->dccg->ref_dppclk = clk_mgr->base.clks.dppclk_khz; 300 int dpp_inst = 0, dppclk_khz, prev_dppclk_khz; local 302 dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz; 306 else if (!context->res_ctx.pipe_ctx[i].plane_res.dpp && dppclk_khz == 0) { 307 /* dpp == NULL && dppclk_khz == 0 is valid because of pipe harvesting. 311 } else if (!context->res_ctx.pipe_ctx[i].plane_res.dpp && dppclk_khz > [all...] |
/openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn10/ |
H A D | rv1_clk_mgr.c | 44 bool request_dpp_div = new_clocks->dispclk_khz > new_clocks->dppclk_khz; 47 bool cur_dpp_div = clk_mgr->base.clks.dispclk_khz > clk_mgr->base.clks.dppclk_khz; 96 bool request_dpp_div = new_clocks->dispclk_khz > new_clocks->dppclk_khz; 124 * 2. request_dpp_div = new_clocks->dispclk_khz > new_clocks->dppclk_khz 186 clk_mgr->base.clks.dppclk_khz = new_clocks->dppclk_khz;
|
/openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/ |
H A D | dcn31_clk_mgr.c | 213 if (new_clocks->dppclk_khz < 100000) 214 new_clocks->dppclk_khz = 100000; 216 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) { 217 if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz) 219 clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz; 236 dcn31_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz); 240 dcn31_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz); [all...] |
/openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/ |
H A D | dcn314_clk_mgr.c | 241 if (new_clocks->dppclk_khz < 100000) 242 new_clocks->dppclk_khz = 100000; 244 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) { 245 if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz) 247 clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz; 264 dcn314_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz); 268 dcn314_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz); [all...] |
/openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/ |
H A D | dcn30_clk_mgr.c | 285 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr_base->clks.dppclk_khz)) { 286 if (clk_mgr_base->clks.dppclk_khz > new_clocks->dppclk_khz) 289 clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz; 290 dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_PIXCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dppclk_khz)); 440 else if (a->dppclk_khz != b->dppclk_khz)
|
/openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/ |
H A D | dcn315_clk_mgr.c | 195 if (new_clocks->dppclk_khz < MIN_DPP_DISP_CLK) 196 new_clocks->dppclk_khz = MIN_DPP_DISP_CLK; 200 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) { 201 if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz) 203 clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz; 223 dcn315_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz); 227 dcn315_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz); [all...] |
/openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/ |
H A D | vg_clk_mgr.c | 154 if (new_clocks->dppclk_khz < 100000) 155 new_clocks->dppclk_khz = 100000; 157 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) { 158 if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz) 160 clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz; 174 dcn301_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz); 178 dcn301_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz); [all...] |
/openbsd-current/sys/dev/pci/drm/amd/display/dc/core/ |
H A D | dc_debug.c | 352 context->bw_ctx.bw.dcn.clk.dppclk_khz, 360 context->bw_ctx.bw.dcn.clk.dppclk_khz,
|
H A D | amdgpu_dc.c | 4657 info->dppClock = (unsigned int)state->bw_ctx.bw.dcn.clk.dppclk_khz;
|
/openbsd-current/sys/dev/pci/drm/amd/display/amdgpu_dm/ |
H A D | amdgpu_dm_trace.h | 495 __field(int, dppclk_khz) 514 __entry->dppclk_khz = clk->dppclk_khz; 531 TP_printk("dispclk_khz=%d dppclk_khz=%d disp_dpp_voltage_level_khz=%d dcfclk_khz=%d socclk_khz=%d " 538 __entry->dppclk_khz,
|
/openbsd-current/sys/dev/pci/drm/amd/display/dc/inc/ |
H A D | core_types.h | 295 int dppclk_khz; member in struct:dcn_fe_bandwidth
|
/openbsd-current/sys/dev/pci/drm/amd/display/dc/dcn10/ |
H A D | dcn10_hw_sequencer.c | 463 "dppclk_khz:%d max_supported_dppclk_khz:%d fclk_khz:%d socclk_khz:%d\n\n", 467 dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz, 1493 if (dc->clk_mgr->clks.dispclk_khz != 0 && dc->clk_mgr->clks.dppclk_khz != 0) { 1495 dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz = dc->clk_mgr->clks.dppclk_khz; 2711 * context->bw_ctx.bw.dcn.clk.dispclk_khz / dppclk_khz. current 2740 context->bw_ctx.bw.dcn.clk.dppclk_khz <= 2752 pipe_ctx->plane_res.bw.dppclk_khz); 2754 dc->clk_mgr->clks.dppclk_khz = should_divided_by_2 ? 3857 current_clocks->dppclk_khz [all...] |
H A D | dcn10_hw_sequencer_debug.c | 479 dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz,
|
/openbsd-current/sys/dev/pci/drm/amd/display/dc/dml/dcn31/ |
H A D | dcn31_fpu.c | 558 context->bw_ctx.bw.dcn.clk.dppclk_khz = 0; 566 context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz = 0;
|
/openbsd-current/sys/dev/pci/drm/amd/display/dc/dml/dcn32/ |
H A D | dcn32_fpu.c | 1375 context->bw_ctx.bw.dcn.clk.dppclk_khz = 0; 1425 if (context->bw_ctx.bw.dcn.clk.dppclk_khz < pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000) 1426 context->bw_ctx.bw.dcn.clk.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000; 1428 context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000; 1430 context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz = 0; 1470 context->bw_ctx.bw.dcn.clk.dppclk_khz = 0; 1479 context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.dppclk_khz;
|
/openbsd-current/sys/dev/pci/drm/amd/display/dc/dml/dcn20/ |
H A D | dcn20_fpu.c | 1166 context->bw_ctx.bw.dcn.clk.dppclk_khz = 0; 1192 if (context->bw_ctx.bw.dcn.clk.dppclk_khz < pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000) 1193 context->bw_ctx.bw.dcn.clk.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000; 1194 context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz = 1210 context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.dppclk_khz;
|
/openbsd-current/sys/dev/pci/drm/amd/display/dc/dml/calcs/ |
H A D | dcn_calcs.c | 1175 context->bw_ctx.bw.dcn.clk.dppclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz / 1420 dc, DM_PP_CLOCK_TYPE_DPPCLK, clocks->dppclk_khz);
|
/openbsd-current/sys/dev/pci/drm/amd/display/dmub/inc/ |
H A D | dmub_cmd.h | 1403 uint32_t dppclk_khz; /**< dppclk kHz */ member in struct:dmub_clocks
|
/openbsd-current/sys/dev/pci/drm/amd/display/dc/ |
H A D | dc.h | 526 int dppclk_khz; member in struct:dc_clocks 564 int bw_dppclk_khz; /*a copy of dppclk_khz*/
|
/openbsd-current/sys/dev/pci/drm/amd/display/dc/dcn20/ |
H A D | dcn20_hwseq.c | 1425 if (old_pipe->plane_res.bw.dppclk_khz != new_pipe->plane_res.bw.dppclk_khz) 1510 dccg->funcs->update_dpp_dto(dccg, dpp->inst, pipe_ctx->plane_res.bw.dppclk_khz);
|
/openbsd-current/sys/dev/pci/drm/amd/display/dc/dcn32/ |
H A D | dcn32_hwseq.c | 743 clocks->dppclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dppclk_mhz * 1000;
|