Searched refs:dppclk_khz (Results 1 - 25 of 25) sorted by relevance

/openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/
H A Ddcn20_clk_mgr.c109 clk_mgr->dccg->ref_dppclk = clk_mgr->base.clks.dppclk_khz;
111 int dpp_inst, dppclk_khz, prev_dppclk_khz; local
117 dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz;
121 if (safe_to_lower || prev_dppclk_khz < dppclk_khz)
123 clk_mgr->dccg, dpp_inst, dppclk_khz);
136 if (clk_mgr->base.clks.dppclk_khz == 0 || clk_mgr->base.clks.dispclk_khz == 0)
140 * clk_mgr->base.dentist_vco_freq_khz / clk_mgr->base.clks.dppclk_khz;
296 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) {
[all...]
/openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn201/
H A Ddcn201_clk_mgr.c139 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) {
140 if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz)
142 clk_mgr->base.clks.dppclk_khz = new_clocks->dppclk_khz;
/openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/
H A Drn_clk_mgr.c114 int dpp_inst, dppclk_khz, prev_dppclk_khz; local
120 dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz;
124 if (safe_to_lower || prev_dppclk_khz < dppclk_khz)
126 clk_mgr->dccg, dpp_inst, dppclk_khz);
187 if (new_clocks->dppclk_khz < 100000 && new_clocks->dppclk_khz > 0)
188 new_clocks->dppclk_khz = 100000;
194 if (new_clocks->dppclk_khz == 0 || new_clocks->dispclk_khz == 0) {
195 new_clocks->dppclk_khz
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/openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/
H A Ddcn316_clk_mgr.c202 if (new_clocks->dppclk_khz < 100000)
203 new_clocks->dppclk_khz = 100000;
207 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) {
208 if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz)
210 clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz;
227 dcn316_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
231 dcn316_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
[all...]
/openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/
H A Ddcn32_clk_mgr.c281 if (new_clocks->dppclk_khz) {
283 * clk_mgr->base.dentist_vco_freq_khz / new_clocks->dppclk_khz;
284 new_clocks->dppclk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR * clk_mgr->base.dentist_vco_freq_khz) / dpp_divider;
298 clk_mgr->dccg->ref_dppclk = clk_mgr->base.clks.dppclk_khz;
300 int dpp_inst = 0, dppclk_khz, prev_dppclk_khz; local
302 dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz;
306 else if (!context->res_ctx.pipe_ctx[i].plane_res.dpp && dppclk_khz == 0) {
307 /* dpp == NULL && dppclk_khz == 0 is valid because of pipe harvesting.
311 } else if (!context->res_ctx.pipe_ctx[i].plane_res.dpp && dppclk_khz >
[all...]
/openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn10/
H A Drv1_clk_mgr.c44 bool request_dpp_div = new_clocks->dispclk_khz > new_clocks->dppclk_khz;
47 bool cur_dpp_div = clk_mgr->base.clks.dispclk_khz > clk_mgr->base.clks.dppclk_khz;
96 bool request_dpp_div = new_clocks->dispclk_khz > new_clocks->dppclk_khz;
124 * 2. request_dpp_div = new_clocks->dispclk_khz > new_clocks->dppclk_khz
186 clk_mgr->base.clks.dppclk_khz = new_clocks->dppclk_khz;
/openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/
H A Ddcn31_clk_mgr.c213 if (new_clocks->dppclk_khz < 100000)
214 new_clocks->dppclk_khz = 100000;
216 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) {
217 if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz)
219 clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz;
236 dcn31_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
240 dcn31_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
[all...]
/openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/
H A Ddcn314_clk_mgr.c241 if (new_clocks->dppclk_khz < 100000)
242 new_clocks->dppclk_khz = 100000;
244 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) {
245 if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz)
247 clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz;
264 dcn314_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
268 dcn314_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
[all...]
/openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/
H A Ddcn30_clk_mgr.c285 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr_base->clks.dppclk_khz)) {
286 if (clk_mgr_base->clks.dppclk_khz > new_clocks->dppclk_khz)
289 clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz;
290 dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_PIXCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dppclk_khz));
440 else if (a->dppclk_khz != b->dppclk_khz)
/openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/
H A Ddcn315_clk_mgr.c195 if (new_clocks->dppclk_khz < MIN_DPP_DISP_CLK)
196 new_clocks->dppclk_khz = MIN_DPP_DISP_CLK;
200 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) {
201 if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz)
203 clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz;
223 dcn315_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
227 dcn315_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
[all...]
/openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/
H A Dvg_clk_mgr.c154 if (new_clocks->dppclk_khz < 100000)
155 new_clocks->dppclk_khz = 100000;
157 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) {
158 if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz)
160 clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz;
174 dcn301_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
178 dcn301_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
[all...]
/openbsd-current/sys/dev/pci/drm/amd/display/dc/core/
H A Ddc_debug.c352 context->bw_ctx.bw.dcn.clk.dppclk_khz,
360 context->bw_ctx.bw.dcn.clk.dppclk_khz,
H A Damdgpu_dc.c4657 info->dppClock = (unsigned int)state->bw_ctx.bw.dcn.clk.dppclk_khz;
/openbsd-current/sys/dev/pci/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm_trace.h495 __field(int, dppclk_khz)
514 __entry->dppclk_khz = clk->dppclk_khz;
531 TP_printk("dispclk_khz=%d dppclk_khz=%d disp_dpp_voltage_level_khz=%d dcfclk_khz=%d socclk_khz=%d "
538 __entry->dppclk_khz,
/openbsd-current/sys/dev/pci/drm/amd/display/dc/inc/
H A Dcore_types.h295 int dppclk_khz; member in struct:dcn_fe_bandwidth
/openbsd-current/sys/dev/pci/drm/amd/display/dc/dcn10/
H A Ddcn10_hw_sequencer.c463 "dppclk_khz:%d max_supported_dppclk_khz:%d fclk_khz:%d socclk_khz:%d\n\n",
467 dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz,
1493 if (dc->clk_mgr->clks.dispclk_khz != 0 && dc->clk_mgr->clks.dppclk_khz != 0) {
1495 dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz = dc->clk_mgr->clks.dppclk_khz;
2711 * context->bw_ctx.bw.dcn.clk.dispclk_khz / dppclk_khz. current
2740 context->bw_ctx.bw.dcn.clk.dppclk_khz <=
2752 pipe_ctx->plane_res.bw.dppclk_khz);
2754 dc->clk_mgr->clks.dppclk_khz = should_divided_by_2 ?
3857 current_clocks->dppclk_khz
[all...]
H A Ddcn10_hw_sequencer_debug.c479 dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz,
/openbsd-current/sys/dev/pci/drm/amd/display/dc/dml/dcn31/
H A Ddcn31_fpu.c558 context->bw_ctx.bw.dcn.clk.dppclk_khz = 0;
566 context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz = 0;
/openbsd-current/sys/dev/pci/drm/amd/display/dc/dml/dcn32/
H A Ddcn32_fpu.c1375 context->bw_ctx.bw.dcn.clk.dppclk_khz = 0;
1425 if (context->bw_ctx.bw.dcn.clk.dppclk_khz < pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000)
1426 context->bw_ctx.bw.dcn.clk.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;
1428 context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;
1430 context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz = 0;
1470 context->bw_ctx.bw.dcn.clk.dppclk_khz = 0;
1479 context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.dppclk_khz;
/openbsd-current/sys/dev/pci/drm/amd/display/dc/dml/dcn20/
H A Ddcn20_fpu.c1166 context->bw_ctx.bw.dcn.clk.dppclk_khz = 0;
1192 if (context->bw_ctx.bw.dcn.clk.dppclk_khz < pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000)
1193 context->bw_ctx.bw.dcn.clk.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;
1194 context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz =
1210 context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.dppclk_khz;
/openbsd-current/sys/dev/pci/drm/amd/display/dc/dml/calcs/
H A Ddcn_calcs.c1175 context->bw_ctx.bw.dcn.clk.dppclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz /
1420 dc, DM_PP_CLOCK_TYPE_DPPCLK, clocks->dppclk_khz);
/openbsd-current/sys/dev/pci/drm/amd/display/dmub/inc/
H A Ddmub_cmd.h1403 uint32_t dppclk_khz; /**< dppclk kHz */ member in struct:dmub_clocks
/openbsd-current/sys/dev/pci/drm/amd/display/dc/
H A Ddc.h526 int dppclk_khz; member in struct:dc_clocks
564 int bw_dppclk_khz; /*a copy of dppclk_khz*/
/openbsd-current/sys/dev/pci/drm/amd/display/dc/dcn20/
H A Ddcn20_hwseq.c1425 if (old_pipe->plane_res.bw.dppclk_khz != new_pipe->plane_res.bw.dppclk_khz)
1510 dccg->funcs->update_dpp_dto(dccg, dpp->inst, pipe_ctx->plane_res.bw.dppclk_khz);
/openbsd-current/sys/dev/pci/drm/amd/display/dc/dcn32/
H A Ddcn32_hwseq.c743 clocks->dppclk_khz = dc->clk_mgr->bw_params->clk_table.entries[0].dppclk_mhz * 1000;

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