Lines Matching refs:dppclk_khz
281 if (new_clocks->dppclk_khz) {
283 * clk_mgr->base.dentist_vco_freq_khz / new_clocks->dppclk_khz;
284 new_clocks->dppclk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR * clk_mgr->base.dentist_vco_freq_khz) / dpp_divider;
298 clk_mgr->dccg->ref_dppclk = clk_mgr->base.clks.dppclk_khz;
300 int dpp_inst = 0, dppclk_khz, prev_dppclk_khz;
302 dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz;
306 else if (!context->res_ctx.pipe_ctx[i].plane_res.dpp && dppclk_khz == 0) {
307 /* dpp == NULL && dppclk_khz == 0 is valid because of pipe harvesting.
311 } else if (!context->res_ctx.pipe_ctx[i].plane_res.dpp && dppclk_khz > 0) {
313 * dppclk_khz > 0.
321 if (safe_to_lower || prev_dppclk_khz < dppclk_khz)
323 clk_mgr->dccg, dpp_inst, dppclk_khz);
604 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr_base->clks.dppclk_khz)) {
605 if (clk_mgr_base->clks.dppclk_khz > new_clocks->dppclk_khz)
608 clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz;
611 dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DPPCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dppclk_khz));
641 dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DPPCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dppclk_khz));
889 else if (a->dppclk_khz != b->dppclk_khz)