/openbsd-current/sys/dev/pci/drm/amd/amdgpu/ |
H A D | lsdma_v6_0.c | 47 WREG32_SOC15(LSDMA, 0, regLSDMA_PIO_SRC_ADDR_LO, lower_32_bits(src_addr)); 48 WREG32_SOC15(LSDMA, 0, regLSDMA_PIO_SRC_ADDR_HI, upper_32_bits(src_addr)); 50 WREG32_SOC15(LSDMA, 0, regLSDMA_PIO_DST_ADDR_LO, lower_32_bits(dst_addr)); 51 WREG32_SOC15(LSDMA, 0, regLSDMA_PIO_DST_ADDR_HI, upper_32_bits(dst_addr)); 53 WREG32_SOC15(LSDMA, 0, regLSDMA_PIO_CONTROL, 0x0); 63 WREG32_SOC15(LSDMA, 0, regLSDMA_PIO_COMMAND, tmp); 80 WREG32_SOC15(LSDMA, 0, regLSDMA_PIO_CONSTFILL_DATA, data); 82 WREG32_SOC15(LSDMA, 0, regLSDMA_PIO_DST_ADDR_LO, lower_32_bits(dst_addr)); 83 WREG32_SOC15(LSDMA, 0, regLSDMA_PIO_DST_ADDR_HI, upper_32_bits(dst_addr)); 85 WREG32_SOC15(LSDM [all...] |
H A D | psp_v12_0.c | 96 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, 99 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, 135 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, 138 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, 160 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 3); 161 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp); 162 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET); 172 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 4); 173 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp); 174 WREG32_SOC15(MP [all...] |
H A D | psp_v11_0_8.c | 39 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, 48 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, 77 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_ring_reg); 80 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_103, psp_ring_reg); 83 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, 104 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg); 107 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg); 110 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg); 114 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg); 163 WREG32_SOC15(MP [all...] |
H A D | psp_v3_1.c | 102 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, 105 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, 141 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, 144 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, 165 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 3); 166 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp); 167 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET); 177 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 4); 178 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp); 179 WREG32_SOC15(MP [all...] |
H A D | gfxhub_v3_0_3.c | 142 WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, 144 WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, 147 WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, 149 WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, 161 WREG32_SOC15(GC, 0, regGCMC_VM_AGP_BASE, 0); 162 WREG32_SOC15(GC, 0, regGCMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); 163 WREG32_SOC15(GC, 0, regGCMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); 166 WREG32_SOC15(GC, 0, regGCMC_VM_SYSTEM_APERTURE_LOW_ADDR, 168 WREG32_SOC15(GC, 0, regGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 174 WREG32_SOC15(G [all...] |
H A D | gfxhub_v2_0.c | 140 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, 142 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, 145 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, 147 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, 157 WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_BASE, 0); 158 WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); 159 WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); 162 WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_LOW_ADDR, 164 WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 169 WREG32_SOC15(G [all...] |
H A D | psp_v13_0_4.c | 116 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, 119 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, 179 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, 182 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, 202 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101, 211 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64, 240 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, psp_ring_reg); 243 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_103, psp_ring_reg); 246 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101, 267 WREG32_SOC15(MP [all...] |
H A D | vcn_v1_0.c | 318 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 320 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 322 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0); 325 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 327 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 330 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 334 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size); 337 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, 339 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, 341 WREG32_SOC15(UV [all...] |
H A D | gfxhub_v1_0.c | 69 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, 71 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, 74 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, 76 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, 79 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, 81 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, 84 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, 86 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, 126 WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 128 WREG32_SOC15(G [all...] |
H A D | nbio_v7_7.c | 33 WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL, 35 WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_REG_FLUSH_CNTL, 53 WREG32_SOC15(NBIO, 0, regBIF_BX1_BIF_FB_EN, 57 WREG32_SOC15(NBIO, 0, regBIF_BX1_BIF_FB_EN, 0); 117 WREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN, reg); 133 WREG32_SOC15(NBIO, 0, 136 WREG32_SOC15(NBIO, 0, 141 WREG32_SOC15(NBIO, 0, regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, 165 WREG32_SOC15(NBIO, 0, regGDC0_BIF_IH_DOORBELL_RANGE, 174 WREG32_SOC15(NBI [all...] |
H A D | mmhub_v2_3.c | 139 WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, 141 WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, 144 WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, 146 WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, 156 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_BASE, 0); 157 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); 158 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); 161 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_LOW_ADDR, 163 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 168 WREG32_SOC15(MMHU [all...] |
H A D | nbio_v4_3.c | 34 WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL, 36 WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_REG_FLUSH_CNTL, 53 WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN, 57 WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN, 0); 99 WREG32_SOC15(NBIO, 0, regS2A_DOORBELL_ENTRY_2_CTRL, doorbell_range); 141 WREG32_SOC15(NBIO, 0, regS2A_DOORBELL_ENTRY_5_CTRL, doorbell_range); 143 WREG32_SOC15(NBIO, 0, regS2A_DOORBELL_ENTRY_4_CTRL, doorbell_range); 148 WREG32_SOC15(NBIO, 0, regS2A_DOORBELL_ENTRY_0_CTRL, 0x30000007); 149 WREG32_SOC15(NBIO, 0, regS2A_DOORBELL_ENTRY_3_CTRL, 0x3000000d); 172 WREG32_SOC15(NBI [all...] |
H A D | mmhub_v3_0.c | 156 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, 158 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, 161 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, 163 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, 181 WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BASE, 0); 182 WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); 183 WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); 186 WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR, 188 WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 194 WREG32_SOC15(MMHU [all...] |
H A D | psp_v10_0.c | 79 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg); 82 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg); 85 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg); 89 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg); 110 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg); 157 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, value);
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H A D | gfxhub_v2_1.c | 143 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, 145 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, 148 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, 150 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, 159 WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_BASE, 0); 160 WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); 161 WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); 164 WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_LOW_ADDR, 166 WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 171 WREG32_SOC15(G [all...] |
H A D | mmhub_v3_0_1.c | 158 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, 160 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, 163 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, 165 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, 175 WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BASE, 0); 176 WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); 177 WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); 185 WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR, 187 WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 193 WREG32_SOC15(MMHU [all...] |
H A D | vcn_v2_0.c | 341 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 343 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 345 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0); 348 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 350 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 353 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 357 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size); 360 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, 362 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, 364 WREG32_SOC15(UV [all...] |
H A D | gfxhub_v3_0.c | 139 WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, 141 WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, 144 WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, 146 WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, 155 WREG32_SOC15(GC, 0, regGCMC_VM_AGP_BASE, 0); 156 WREG32_SOC15(GC, 0, regGCMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); 157 WREG32_SOC15(GC, 0, regGCMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); 161 WREG32_SOC15(GC, 0, regGCMC_VM_SYSTEM_APERTURE_LOW_ADDR, 163 WREG32_SOC15(GC, 0, regGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 169 WREG32_SOC15(G [all...] |
H A D | df_v1_7.c | 51 WREG32_SOC15(DF, 0, mmFabricConfigAccessControl, tmp); 53 WREG32_SOC15(DF, 0, mmFabricConfigAccessControl, 89 WREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater, tmp); 94 WREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater, tmp);
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H A D | mmhub_v3_0_2.c | 149 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, 151 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, 154 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, 156 WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, 166 WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BASE, 0); 167 WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); 168 WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); 177 WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR, 179 WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 186 WREG32_SOC15(MMHU [all...] |
H A D | mmhub_v1_8.c | 95 WREG32_SOC15(MMHUB, i, 98 WREG32_SOC15(MMHUB, i, 102 WREG32_SOC15(MMHUB, i, 105 WREG32_SOC15(MMHUB, i, 110 WREG32_SOC15(MMHUB, i, 113 WREG32_SOC15(MMHUB, i, 117 WREG32_SOC15(MMHUB, i, 120 WREG32_SOC15(MMHUB, i, 139 WREG32_SOC15(MMHUB, i, regMC_VM_AGP_BASE, 0); 140 WREG32_SOC15(MMHU [all...] |
H A D | mmhub_v2_0.c | 230 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_LOW_ADDR, 232 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 238 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 240 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, 244 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32, 246 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, 252 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL2, tmp); 271 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL, tmp); 296 WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL, tmp); 301 WREG32_SOC15(MMHU [all...] |
H A D | gfx_v9_4.c | 695 WREG32_SOC15(GC, 0, mmVML2_MEM_ECC_INDEX, 255); 696 WREG32_SOC15(GC, 0, mmVML2_MEM_ECC_CNTL, 0); 697 WREG32_SOC15(GC, 0, mmVML2_WALKER_MEM_ECC_INDEX, 255); 698 WREG32_SOC15(GC, 0, mmVML2_WALKER_MEM_ECC_CNTL, 0); 699 WREG32_SOC15(GC, 0, mmUTCL2_MEM_ECC_INDEX, 255); 700 WREG32_SOC15(GC, 0, mmUTCL2_MEM_ECC_CNTL, 0); 702 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_DSM_INDEX, 255); 703 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_DSM_CNTL, 0); 704 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_DSM_INDEX, 255); 705 WREG32_SOC15(G [all...] |
H A D | psp_v13_0.c | 224 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, 227 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, 293 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, 296 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, 316 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101, 325 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64, 354 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, psp_ring_reg); 357 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_103, psp_ring_reg); 360 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101, 381 WREG32_SOC15(MP [all...] |
/openbsd-current/sys/dev/pci/drm/amd/pm/powerplay/smumgr/ |
H A D | smu9_smumgr.c | 99 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_101, msg); 101 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66, msg); 121 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_103, 0); 123 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0); 150 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_103, 0); 151 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_102, parameter); 153 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0); 154 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82, parameter);
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