amd/amdgpu/mmhub_v1_8.c

95 			WREG32_SOC15(MMHUB, i,
98 			WREG32_SOC15(MMHUB, i,
102 			WREG32_SOC15(MMHUB, i,
105 			WREG32_SOC15(MMHUB, i,
110 			WREG32_SOC15(MMHUB, i,
113 			WREG32_SOC15(MMHUB, i,
117 			WREG32_SOC15(MMHUB, i,
120 			WREG32_SOC15(MMHUB, i,
139 		WREG32_SOC15(MMHUB, i, regMC_VM_AGP_BASE, 0);
140 		WREG32_SOC15(MMHUB, i, regMC_VM_AGP_BOT,
142 		WREG32_SOC15(MMHUB, i, regMC_VM_AGP_TOP,
146 		WREG32_SOC15(MMHUB, i, regMC_VM_SYSTEM_APERTURE_LOW_ADDR,
149 		WREG32_SOC15(MMHUB, i, regMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
156 			WREG32_SOC15(MMHUB, i, regMC_VM_AGP_BOT, 0xFFFFFF);
157 			WREG32_SOC15(MMHUB, i, regMC_VM_AGP_TOP, 0);
158 			WREG32_SOC15(MMHUB, i, regMC_VM_FB_LOCATION_TOP, 0);
159 			WREG32_SOC15(MMHUB, i, regMC_VM_FB_LOCATION_BASE,
161 			WREG32_SOC15(MMHUB, i,
164 			WREG32_SOC15(MMHUB, i,
170 		WREG32_SOC15(MMHUB, i, regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
172 		WREG32_SOC15(MMHUB, i, regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
176 		WREG32_SOC15(MMHUB, i,
179 		WREG32_SOC15(MMHUB, i,
186 		WREG32_SOC15(MMHUB, i, regVM_L2_PROTECTION_FAULT_CNTL2, tmp);
212 		WREG32_SOC15(MMHUB, i, regMC_VM_MX_L1_TLB_CNTL, tmp);
240 		WREG32_SOC15(MMHUB, i, regVM_L2_CNTL, tmp);
246 		WREG32_SOC15(MMHUB, i, regVM_L2_CNTL2, tmp);
258 		WREG32_SOC15(MMHUB, i, regVM_L2_CNTL3, tmp);
273 		WREG32_SOC15(MMHUB, i, regVM_L2_CNTL4, tmp);
293 		WREG32_SOC15(MMHUB, i, regVM_CONTEXT0_CNTL, tmp);
307 		WREG32_SOC15(MMHUB, i,
310 		WREG32_SOC15(MMHUB, i,
314 		WREG32_SOC15(MMHUB, i,
317 		WREG32_SOC15(MMHUB, i,
321 		WREG32_SOC15(MMHUB, i,
323 		WREG32_SOC15(MMHUB, i,
450 		WREG32_SOC15(MMHUB, j, regMC_VM_MX_L1_TLB_CNTL, tmp);
457 			WREG32_SOC15(MMHUB, j, regVM_L2_CNTL, tmp);
458 			WREG32_SOC15(MMHUB, j, regVM_L2_CNTL3, 0);
510 		WREG32_SOC15(MMHUB, i, regVM_L2_PROTECTION_FAULT_CNTL, tmp);
803 	WREG32_SOC15(MMHUB, mmhub_inst, regMM_CANE_ICG_CTRL, reg_value);
809 	WREG32_SOC15(MMHUB, mmhub_inst, regMM_CANE_ERR_STATUS, reg_value);
815 	WREG32_SOC15(MMHUB, mmhub_inst, regMM_CANE_ICG_CTRL, reg_value);