Lines Matching refs:WREG32_SOC15
33 WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL,
35 WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_REG_FLUSH_CNTL,
53 WREG32_SOC15(NBIO, 0, regBIF_BX1_BIF_FB_EN,
57 WREG32_SOC15(NBIO, 0, regBIF_BX1_BIF_FB_EN, 0);
117 WREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN, reg);
133 WREG32_SOC15(NBIO, 0,
136 WREG32_SOC15(NBIO, 0,
141 WREG32_SOC15(NBIO, 0, regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
165 WREG32_SOC15(NBIO, 0, regGDC0_BIF_IH_DOORBELL_RANGE,
174 WREG32_SOC15(NBIO, 0, regBIF_BX1_INTERRUPT_CNTL2,
189 WREG32_SOC15(NBIO, 0, regBIF_BX1_INTERRUPT_CNTL, interrupt_cntl);
248 WREG32_SOC15(NBIO, 0, regBIF0_PCIE_MST_CTRL_3, data);
278 WREG32_SOC15(NBIO, 0, regBIF0_CPM_CONTROL, data);
296 WREG32_SOC15(NBIO, 0, regBIF0_PCIE_CNTL2, data);
308 WREG32_SOC15(NBIO, 0, regBIF0_PCIE_TX_POWER_CTRL_1, data);