/openbsd-current/sys/arch/luna88k/luna88k/ |
H A D | pmap_table.c | 38 #define RW (PROT_READ | PROT_WRITE) macro 50 { NVRAM_ADDR, NVRAM_SPACE, RW, CI }, 51 { NVRAM_ADDR_88K2, PAGE_SIZE, RW, CI }, 52 { OBIO_PIO0_BASE, PAGE_SIZE, RW, CI }, 53 { OBIO_PIO1_BASE, PAGE_SIZE, RW, CI }, 54 { OBIO_SIO, PAGE_SIZE, RW, CI }, 55 { OBIO_TAS, PAGE_SIZE, RW, CI }, 56 { OBIO_CLOCK0, PAGE_SIZE, RW, CI }, 57 { INT_ST_MASK0, PAGE_SIZE, RW, CI }, 58 { SOFT_INT0, PAGE_SIZE, RW, C [all...] |
/openbsd-current/sys/dev/ic/ |
H A D | ar9285.c | 208 reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF, modal->iqCalI); 209 reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF, modal->iqCalQ); 214 reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN, 216 reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_DB, 218 reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN, 220 reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN2_DB, 226 reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN, 228 reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_DB, 230 reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN, 232 reg = RW(re [all...] |
H A D | ar9380.c | 312 reg = RW(reg, AR9485_PHY_65NM_CH0_TOP2_XPABIASLVL, 317 reg = RW(reg, AR_PHY_65NM_CH0_TOP_XPABIASLVL, 321 reg = RW(reg, AR_PHY_65NM_CH0_THERM_XPABIASLVL_MSB, 329 reg = RW(reg, AR_SWITCH_TABLE_COM_ALL, modal->antCtrlCommon); 332 reg = RW(reg, AR_SWITCH_TABLE_COM_2_ALL, modal->antCtrlCommon2); 338 reg = RW(reg, AR_SWITCH_TABLE_ALL, modal->antCtrlChain[i]); 345 reg = RW(reg, AR_PHY_MC_GAIN_CTRL_ANT_DIV_CTRL_ALL, 363 reg = RW(reg, AR_PHY_65NM_CH0_BIAS1_0, 5); 364 reg = RW(reg, AR_PHY_65NM_CH0_BIAS1_1, 5); 365 reg = RW(re [all...] |
H A D | ar9287.c | 185 reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF, 187 reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF, 192 reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN, 194 reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_DB, 199 reg = RW(reg, AR9280_PHY_RXGAIN_TXRX_MARGIN, 201 reg = RW(reg, AR9280_PHY_RXGAIN_TXRX_ATTEN, 208 reg = RW(reg, AR_PHY_SETTLING_SWITCH, modal->swSettleHt40); 210 reg = RW(reg, AR_PHY_SETTLING_SWITCH, modal->switchSettling); 214 reg = RW(reg, AR_PHY_DESIRED_SZ_ADC, modal->adcDesiredSize); 224 reg = RW(re [all...] |
H A D | ar9280.c | 228 reg = RW(reg, AR_AN_SYNTH9_REFDIVA, 1); 264 reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF, 266 reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF, 272 reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN, 274 reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_DB, 276 reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN, 278 reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN2_DB, 287 reg = RW(reg, AR9280_PHY_RXGAIN_TXRX_ATTEN, 289 reg = RW(reg, AR9280_PHY_RXGAIN_TXRX_MARGIN, 295 reg = RW(re [all...] |
H A D | ar5416.c | 262 reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF, 264 reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF, 273 reg = RW(reg, AR_PHY_GAIN_2GHZ_BSW_MARGIN, 275 reg = RW(reg, AR_PHY_GAIN_2GHZ_BSW_ATTEN, 284 reg = RW(reg, AR_PHY_RXGAIN_TXRX_ATTEN, txRxAtten); 288 reg = RW(reg, AR_PHY_GAIN_2GHZ_RXTX_MARGIN, 293 reg = RW(reg, AR_PHY_SETTLING_SWITCH, modal->switchSettling); 297 reg = RW(reg, AR_PHY_DESIRED_SZ_ADC, modal->adcDesiredSize); 298 reg = RW(reg, AR_PHY_DESIRED_SZ_PGA, modal->pgaDesiredSize); 308 reg = RW(re [all...] |
H A D | ar9003.c | 564 reg = RW(reg, AR_GPIO_INPUT_MUX2_RFSILENT, 0); 820 reg = RW(reg, AR_RXBP_THRESH_HP, 1); 821 reg = RW(reg, AR_RXBP_THRESH_LP, 1); 1864 reg = RW(reg, AR_PHY_TIMING3_DSC_EXP, exp); 1865 reg = RW(reg, AR_PHY_TIMING3_DSC_MAN, man); 1874 reg = RW(reg, AR_PHY_SGI_DSC_EXP, exp); 1875 reg = RW(reg, AR_PHY_SGI_DSC_MAN, man); 1966 reg = RW(reg, AR_PHY_MAXCCA_PWR, nf[i]); 1970 reg = RW(reg, AR_PHY_EXT_MAXCCA_PWR, nf_ext[i]); 2125 reg = RW(re [all...] |
H A D | ar5008.c | 462 reg = RW(reg, AR_GPIO_INPUT_MUX2_RFSILENT, 0); 1926 reg = RW(reg, AR_PHY_TIMING3_DSC_EXP, exp); 1927 reg = RW(reg, AR_PHY_TIMING3_DSC_MAN, man); 1936 reg = RW(reg, AR_PHY_HALFGI_DSC_EXP, exp); 1937 reg = RW(reg, AR_PHY_HALFGI_DSC_MAN, man); 2032 reg = RW(reg, AR_PHY_MAXCCA_PWR, nf[i]); 2036 reg = RW(reg, AR_PHY_EXT_MAXCCA_PWR, nf_ext[i]); 2150 reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX, log); 2237 reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF, i_coff); 2238 reg = RW(re [all...] |
H A D | rtwn.c | 477 RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) | 510 reg = RW(reg, R92C_EFUSE_CTRL_ADDR, addr); 541 reg = RW(reg, R92C_EFUSE_TEST_SEL, 0); 906 reg = RW(reg, R92C_RRSR_RATE_BITMAP, rates); 1118 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1123 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1144 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 1149 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 2091 reg = RW(reg, R92C_TXAGC_A_CCK1, power[RTWN_POWER_CCK1]); 2094 reg = RW(re [all...] |
/openbsd-current/usr.bin/uuencode/ |
H A D | uuencode.c | 114 #define RW (S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP|S_IROTH|S_IWOTH) macro 115 mode = RW & ~umask(RW);
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/openbsd-current/gnu/llvm/compiler-rt/lib/tsan/tests/rtl/ |
H A D | tsan_test_util_posix.cpp | 107 else if (type_ == RW) 130 else if (type_ == RW) 142 else if (type_ == RW) 154 else if (type_ == RW) 167 else if (type_ == RW) 173 CHECK(type_ == RW); 179 CHECK(type_ == RW); 185 CHECK(type_ == RW);
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H A D | tsan_test_util.h | 42 RW, enumerator in enum:UserMutex::Type
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H A D | tsan_mop.cpp | 68 UserMutex m(UserMutex::RW); 87 UserMutex m(UserMutex::RW);
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H A D | tsan_mutex.cpp | 59 UserMutex m(UserMutex::RW); 127 UserMutex m(UserMutex::RW);
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/openbsd-current/usr.sbin/lpr/common_source/ |
H A D | lp.h | 66 extern long RW; /* open LP for reading and writing */
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/openbsd-current/gnu/llvm/llvm/lib/MC/MCDisassembler/ |
H A D | MCDisassembler.cpp | 65 SMC_PCASE(RW, 1)
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/openbsd-current/gnu/llvm/llvm/lib/Target/Hexagon/ |
H A D | HexagonBitTracker.cpp | 94 uint16_t RW = getRegBitWidth(RegisterRef(Reg, Sub)); local 101 return IsSubLo ? BT::BitMask(0, RW-1) 102 : BT::BitMask(RW, 2*RW-1); 274 // Extract RW low bits of the cell. 275 auto lo = [this] (const BT::RegisterCell &RC, uint16_t RW) 277 assert(RW <= RC.width()); 278 return eXTR(RC, 0, RW); 280 // Extract RW high bits of the cell. 281 auto hi = [this] (const BT::RegisterCell &RC, uint16_t RW) [all...] |
H A D | HexagonBitSimplify.cpp | 1587 unsigned RW = RC.width(); 1588 if (W == RW) { 1602 if (W*2 != RW) 2431 unsigned RW = W; 2491 if (Len == RW) 2514 if (SW < RW || (SW % RW) != 0) 2522 unsigned OE = (Off+Len)/RW; 2523 if (OE != Off/RW) { 2526 // size RW, an [all...] |
/openbsd-current/gnu/llvm/clang/utils/ABITest/ |
H A D | Enumeration.py | 152 LW,RW = W//2, W - (W//2) 153 L,R = getNthPairBounded(N, H**LW, H**RW) 155 getNthNTuple(R,RW,H=H,useLeftToRight=useLeftToRight))
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/openbsd-current/sys/dev/microcode/aic7xxx/ |
H A D | aicasm_symbol.h | 72 RW = 0x03 enumerator in enum:__anon9087
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H A D | aicasm_scan.l | 168 RW|RO|WO { 169 if (strcmp(yytext, "RW") == 0) 170 yylval.value = RW;
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/openbsd-current/gnu/llvm/lldb/source/Plugins/Instruction/ARM64/ |
H A D | EmulateInstructionARM64.h | 147 RW : 1, // Current register width ��� 0 is AArch64, 1 is AArch32 member in struct:EmulateInstructionARM64::__anon1353
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/openbsd-current/libexec/getty/ |
H A D | gettytab.h | 141 #define RW gettyflags[11].value macro
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/openbsd-current/gnu/llvm/llvm/lib/CodeGen/ |
H A D | MLRegallocEvictAdvisor.cpp | 260 double RW = 0; member in struct:__anon2115::LIFeatureComponents 806 Ret.RW += (Reads && Writes) * Freq; 834 double RW = 0.0; local 870 RW += LIFC.RW; 912 SET(weighed_read_writes_by_max, float, RW);
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/openbsd-current/gnu/llvm/llvm/utils/TableGen/ |
H A D | CodeGenSchedule.cpp | 585 // Visit each RW in the sequence selected by the current variant. 609 for (Record *RW : RWs) { 610 if (RW->isSubClassOf("SchedWrite")) 611 scanSchedRW(RW, SWDefs, RWSet); 613 assert(RW->isSubClassOf("SchedRead") && "Unknown SchedReadWrite"); 614 scanSchedRW(RW, SRDefs, RWSet); 689 CodeGenSchedRW &RW = getSchedRW(MatchDef); local 690 if (RW.IsAlias) 692 RW.Aliases.push_back(ADef); 732 RWVec, [Def](const CodeGenSchedRW &RW) { retur [all...] |