1/*	$OpenBSD: pmap_table.c,v 1.14 2017/03/20 19:42:51 miod Exp $	*/
2
3/*
4 * Mach Operating System
5 * Copyright (c) 1993-1992 Carnegie Mellon University
6 * All Rights Reserved.
7 *
8 * Permission to use, copy, modify and distribute this software and its
9 * documentation is hereby granted, provided that both the copyright
10 * notice and this permission notice appear in all copies of the
11 * software, derivative works or modified versions, and any portions
12 * thereof, and that both notices appear in supporting documentation.
13 *
14 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
15 * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
16 * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
17 *
18 * Carnegie Mellon requests users of this software to return to
19 *
20 *  Software Distribution Coordinator  or  Software.Distribution@CS.CMU.EDU
21 *  School of Computer Science
22 *  Carnegie Mellon University
23 *  Pittsburgh PA 15213-3890
24 *
25 * any improvements or extensions that they make and grant Carnegie Mellon
26 * the rights to redistribute these changes.
27 */
28
29#include <sys/param.h>
30#include <sys/systm.h>
31
32#include <uvm/uvm_extern.h>
33
34#include <machine/board.h>
35#include <machine/pmap_table.h>
36
37#define	R	PROT_READ
38#define	RW	(PROT_READ | PROT_WRITE)
39#define	CW	CACHE_WT
40#define	CI	CACHE_INH
41#define	CG	CACHE_GLOBAL
42
43/*  start, size, prot, cacheability */
44const struct pmap_table
45luna88k_board_table[] = {
46#if 0
47	{ PROM_ADDR,		PROM_SPACE,		R,	CI },
48#endif
49	{ FUSE_ROM_ADDR,	FUSE_ROM_SPACE,		R,	CI },
50	{ NVRAM_ADDR,		NVRAM_SPACE,		RW,	CI },
51	{ NVRAM_ADDR_88K2,	PAGE_SIZE,		RW,	CI },
52	{ OBIO_PIO0_BASE,	PAGE_SIZE,		RW,	CI },
53	{ OBIO_PIO1_BASE,	PAGE_SIZE,		RW,	CI },
54	{ OBIO_SIO,		PAGE_SIZE,		RW,	CI },
55	{ OBIO_TAS,		PAGE_SIZE,		RW,	CI },
56	{ OBIO_CLOCK0,		PAGE_SIZE,		RW,	CI },
57	{ INT_ST_MASK0,		PAGE_SIZE,		RW,	CI },
58	{ SOFT_INT0,		PAGE_SIZE,		RW,	CI },
59	{ SOFT_INT_FLAG0,	PAGE_SIZE,		RW,	CI },
60	{ RESET_CPU0,		PAGE_SIZE,		RW,	CI },
61	{ TRI_PORT_RAM,		TRI_PORT_RAM_SPACE,	RW,	CI },
62#if 0
63	{ EXT_A_ADDR,		EXT_A_SPACE,		RW,	CI },
64	{ EXT_B_ADDR,		EXT_B_SPACE,		RW,	CI },
65#endif
66	{ PC_BASE,		PC_SPACE,		RW,	CI },
67#if 0
68	{ MROM_ADDR,		MROM_SPACE,		R,	CI },
69#endif
70	{ BMAP_RFCNT,		PAGE_SIZE,		RW,	CI },
71	{ BMAP_BMSEL,		PAGE_SIZE,		RW,	CI },
72	{ BMAP_BMP,		BMAP_BMAP0 - BMAP_BMP,	RW,	CI, TRUE },
73	{ BMAP_BMAP0,		BMAP_BMAP1 - BMAP_BMAP0, RW,	CI, TRUE },
74	{ BMAP_BMAP1,		BMAP_BMAP2 - BMAP_BMAP1, RW,	CI, TRUE },
75	{ BMAP_BMAP2,		BMAP_BMAP3 - BMAP_BMAP2, RW,	CI, TRUE },
76	{ BMAP_BMAP3,		BMAP_BMAP4 - BMAP_BMAP3, RW,	CI, TRUE },
77	{ BMAP_BMAP4,		BMAP_BMAP5 - BMAP_BMAP4, RW,	CI, TRUE },
78	{ BMAP_BMAP5,		BMAP_BMAP6 - BMAP_BMAP5, RW,	CI, TRUE },
79	{ BMAP_BMAP6,		BMAP_BMAP7 - BMAP_BMAP6, RW,	CI, TRUE },
80	{ BMAP_BMAP7,		BMAP_FN - BMAP_BMAP7,	RW,	CI, TRUE },
81	{ BMAP_FN,		PAGE_SIZE,		RW,	CI },
82#if 0
83	{ BMAP_FN0,		PAGE_SIZE,		RW,	CI },
84	{ BMAP_FN1,		PAGE_SIZE,		RW,	CI },
85	{ BMAP_FN2,		PAGE_SIZE,		RW,	CI },
86	{ BMAP_FN3,		PAGE_SIZE,		RW,	CI },
87	{ BMAP_FN4,		PAGE_SIZE,		RW,	CI },
88	{ BMAP_FN5,		PAGE_SIZE,		RW,	CI },
89	{ BMAP_FN6,		PAGE_SIZE,		RW,	CI },
90	{ BMAP_FN7,		PAGE_SIZE,		RW,	CI },
91	{ BMAP_PALLET0,		PAGE_SIZE,		RW,	CI },
92	{ BMAP_PALLET1,		PAGE_SIZE,		RW,	CI },
93#endif
94	{ BMAP_PALLET2,		PAGE_SIZE,		RW,	CI },
95#if 0
96	{ BOARD_CHECK_REG,	PAGE_SIZE,		RW,	CI },
97	{ BMAP_CRTC,		PAGE_SIZE,		RW,	CI },
98#endif
99	{ SCSI_ADDR,		PAGE_SIZE,		RW,	CI },
100	{ LANCE_ADDR,		PAGE_SIZE,		RW,	CI },
101	{ 0,			0xffffffff,		0,	0 },
102};
103
104const struct pmap_table *
105pmap_table_build()
106{
107	return luna88k_board_table;
108}
109