Searched refs:ppc_cached_irq_mask (Results 1 - 13 of 13) sorted by relevance

/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/arch/ppc/syslib/
H A Dppc403_pic.c79 ppc_cached_irq_mask[word] |= (1 << (31 - bit));
80 mtdcr(DCRN_EXIER, ppc_cached_irq_mask[word]);
91 ppc_cached_irq_mask[word] &= ~(1 << (31 - bit));
92 mtdcr(DCRN_EXIER, ppc_cached_irq_mask[word]);
103 ppc_cached_irq_mask[word] &= ~(1 << (31 - bit));
104 mtdcr(DCRN_EXIER, ppc_cached_irq_mask[word]);
117 ppc_cached_irq_mask[0] = 0;
119 mtdcr(DCRN_EXIER, ppc_cached_irq_mask[0]);
H A Dppc8xx_pic.c31 ppc_cached_irq_mask[word] &= ~(1 << (31-bit));
32 out_be32(&((immap_t *)IMAP_ADDR)->im_siu_conf.sc_simask, ppc_cached_irq_mask[word]);
42 ppc_cached_irq_mask[word] |= (1 << (31-bit));
43 out_be32(&((immap_t *)IMAP_ADDR)->im_siu_conf.sc_simask, ppc_cached_irq_mask[word]);
55 ppc_cached_irq_mask[word] |= (1 << (31-bit));
56 out_be32(&((immap_t *)IMAP_ADDR)->im_siu_conf.sc_simask, ppc_cached_irq_mask[word]);
68 ppc_cached_irq_mask[word] &= ~(1 << (31-bit));
69 out_be32(&((immap_t *)IMAP_ADDR)->im_siu_conf.sc_simask, ppc_cached_irq_mask[word]);
H A Dcpm2_pic.c59 ppc_cached_irq_mask[word] &= ~(1 << bit);
60 simr[word] = ppc_cached_irq_mask[word];
74 ppc_cached_irq_mask[word] |= 1 << bit;
75 simr[word] = ppc_cached_irq_mask[word];
90 ppc_cached_irq_mask[word] &= ~(1 << bit);
91 simr[word] = ppc_cached_irq_mask[word];
108 ppc_cached_irq_mask[word] |= 1 << bit;
109 simr[word] = ppc_cached_irq_mask[word];
H A Dcpc700_pic.c45 /* Know IRQ fits in entry 0 of ppc_cached_irq_mask[] */
46 ppc_cached_irq_mask[0] |= CPC700_UIC_IRQ_BIT(irq);
48 CPC700_OUT_32(CPC700_UIC_UICER, ppc_cached_irq_mask[0]);
61 /* Know IRQ fits in entry 0 of ppc_cached_irq_mask[] */
62 ppc_cached_irq_mask[0] &=
65 CPC700_OUT_32(CPC700_UIC_UICER, ppc_cached_irq_mask[0]);
80 /* Know IRQ fits in entry 0 of ppc_cached_irq_mask[] */
83 ppc_cached_irq_mask[0] &= ~bit;
84 CPC700_OUT_32(CPC700_UIC_UICER, ppc_cached_irq_mask[0]);
133 ppc_cached_irq_mask[
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H A Dgt64260_pic.c89 ppc_cached_irq_mask[0] = 0;
90 ppc_cached_irq_mask[1] = 0x0f000000; /* Enable GPP intrs */
91 ppc_cached_irq_mask[2] = 0;
94 mv64x60_write(&bh, MV64x60_GPP_INTR_MASK, ppc_cached_irq_mask[2]);
96 mv64x60_write(&bh, GT64260_IC_CPU_INTR_MASK_LO, ppc_cached_irq_mask[0]);
97 mv64x60_write(&bh, GT64260_IC_CPU_INTR_MASK_HI, ppc_cached_irq_mask[1]);
126 irq = __ilog2((irq & 0x3dfffffe) & ppc_cached_irq_mask[0]);
130 irq = __ilog2((irq & 0x0f000db7) & ppc_cached_irq_mask[1]);
139 ppc_cached_irq_mask[2]);
183 ppc_cached_irq_mask[
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H A Dmv64360_pic.c108 ppc_cached_irq_mask[0] = 0;
109 ppc_cached_irq_mask[1] = 0x0f000000; /* Enable GPP intrs */
110 ppc_cached_irq_mask[2] = 0;
114 mv64x60_write(&bh, MV64x60_GPP_INTR_MASK, ppc_cached_irq_mask[2]);
115 mv64x60_write(&bh, MV64360_IC_CPU0_INTR_MASK_LO,ppc_cached_irq_mask[0]);
116 mv64x60_write(&bh, MV64360_IC_CPU0_INTR_MASK_HI,ppc_cached_irq_mask[1]);
161 irq = __ilog2((irq & 0x3dfffffe) & ppc_cached_irq_mask[0]);
165 irq = __ilog2((irq & 0x1f0003f7) & ppc_cached_irq_mask[1]);
174 ppc_cached_irq_mask[2]);
227 ppc_cached_irq_mask[
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H A Dppc4xx_pic.c46 ppc_cached_irq_mask[n] |= mask; \
47 mtdcr(DCRN_UIC_ER(UIC##n), ppc_cached_irq_mask[n]); \
52 ppc_cached_irq_mask[n] &= ~IRQ_MASK_UIC##n(irq); \
53 mtdcr(DCRN_UIC_ER(UIC##n), ppc_cached_irq_mask[n]); \
60 ppc_cached_irq_mask[n] &= ~mask; \
61 mtdcr(DCRN_UIC_ER(UIC##n), ppc_cached_irq_mask[n]); \
75 ppc_cached_irq_mask[n] |= mask; \
76 mtdcr(DCRN_UIC_ER(UIC##n), ppc_cached_irq_mask[n]); \
115 ppc_cached_irq_mask[0] |= UIC0_UIC1NC | UIC0_UIC2NC | UIC0_UIC3NC;
117 mtdcr(DCRN_UIC_ER(UIC0), ppc_cached_irq_mask[ local
175 mtdcr(DCRN_UIC_ER(UIC0), ppc_cached_irq_mask[0]); local
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/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/arch/powerpc/sysdev/
H A Dmpc8xx_pic.c25 static unsigned long ppc_cached_irq_mask[NR_MASK_WORDS]; variable
38 ppc_cached_irq_mask[word] |= (1 << (31-bit));
39 out_be32(&siu_reg->sc_simask, ppc_cached_irq_mask[word]);
50 ppc_cached_irq_mask[word] &= ~(1 << (31-bit));
51 out_be32(&siu_reg->sc_simask, ppc_cached_irq_mask[word]);
71 ppc_cached_irq_mask[word] |= (1 << (31-bit));
72 out_be32(&siu_reg->sc_simask, ppc_cached_irq_mask[word]);
H A Dcpm2_pic.c56 static unsigned long ppc_cached_irq_mask[NR_MASK_WORDS]; variable
90 ppc_cached_irq_mask[word] &= ~(1 << bit);
91 out_be32(&cpm2_intctl->ic_simrh + word, ppc_cached_irq_mask[word]);
102 ppc_cached_irq_mask[word] |= 1 << bit;
103 out_be32(&cpm2_intctl->ic_simrh + word, ppc_cached_irq_mask[word]);
128 ppc_cached_irq_mask[word] |= 1 << bit;
129 out_be32(&cpm2_intctl->ic_simrh + word, ppc_cached_irq_mask[word]);
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/arch/powerpc/platforms/powermac/
H A Dpic.c65 static unsigned long ppc_cached_irq_mask[NR_MASK_WORDS]; variable
90 __clear_bit(src, ppc_cached_irq_mask);
93 out_le32(&pmac_irq_hw[i]->enable, ppc_cached_irq_mask[i]);
100 != (ppc_cached_irq_mask[i] & bit));
128 out_le32(&pmac_irq_hw[i]->enable, ppc_cached_irq_mask[i]);
135 != (ppc_cached_irq_mask[i] & bit));
142 if (bit & ppc_cached_irq_mask[i] & in_le32(&pmac_irq_hw[i]->level))
159 __set_bit(src, ppc_cached_irq_mask);
172 __clear_bit(src, ppc_cached_irq_mask);
183 __set_bit(src, ppc_cached_irq_mask);
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/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/arch/ppc/platforms/
H A Dprep_setup.c94 #define cached_21 (((char *)(ppc_cached_irq_mask))[3])
95 #define cached_A1 (((char *)(ppc_cached_irq_mask))[2])
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/arch/powerpc/kernel/
H A Dirq.c82 unsigned long ppc_cached_irq_mask[NR_MASK_WORDS]; variable
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/include/asm-powerpc/
H A Dirq.h773 extern unsigned long ppc_cached_irq_mask[NR_MASK_WORDS];

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