1/* 2 * Support for the interrupt controllers found on Power Macintosh, 3 * currently Apple's "Grand Central" interrupt controller in all 4 * it's incarnations. OpenPIC support used on newer machines is 5 * in a separate file 6 * 7 * Copyright (C) 1997 Paul Mackerras (paulus@samba.org) 8 * Copyright (C) 2005 Benjamin Herrenschmidt (benh@kernel.crashing.org) 9 * IBM, Corp. 10 * 11 * This program is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License 13 * as published by the Free Software Foundation; either version 14 * 2 of the License, or (at your option) any later version. 15 * 16 */ 17 18#include <linux/stddef.h> 19#include <linux/init.h> 20#include <linux/sched.h> 21#include <linux/signal.h> 22#include <linux/pci.h> 23#include <linux/interrupt.h> 24#include <linux/sysdev.h> 25#include <linux/adb.h> 26#include <linux/pmu.h> 27#include <linux/module.h> 28 29#include <asm/sections.h> 30#include <asm/io.h> 31#include <asm/smp.h> 32#include <asm/prom.h> 33#include <asm/pci-bridge.h> 34#include <asm/time.h> 35#include <asm/pmac_feature.h> 36#include <asm/mpic.h> 37 38#include "pmac.h" 39 40extern irqreturn_t xmon_irq(int, void *); 41 42#ifdef CONFIG_PPC32 43struct pmac_irq_hw { 44 unsigned int event; 45 unsigned int enable; 46 unsigned int ack; 47 unsigned int level; 48}; 49 50/* Default addresses */ 51static volatile struct pmac_irq_hw __iomem *pmac_irq_hw[4]; 52 53#define GC_LEVEL_MASK 0x3ff00000 54#define OHARE_LEVEL_MASK 0x1ff00000 55#define HEATHROW_LEVEL_MASK 0x1ff00000 56 57static int max_irqs; 58static int max_real_irqs; 59static u32 level_mask[4]; 60 61static DEFINE_SPINLOCK(pmac_pic_lock); 62 63#define NR_MASK_WORDS ((NR_IRQS + 31) / 32) 64static unsigned long ppc_lost_interrupts[NR_MASK_WORDS]; 65static unsigned long ppc_cached_irq_mask[NR_MASK_WORDS]; 66static int pmac_irq_cascade = -1; 67static struct irq_host *pmac_pic_host; 68 69static void __pmac_retrigger(unsigned int irq_nr) 70{ 71 if (irq_nr >= max_real_irqs && pmac_irq_cascade > 0) { 72 __set_bit(irq_nr, ppc_lost_interrupts); 73 irq_nr = pmac_irq_cascade; 74 mb(); 75 } 76 if (!__test_and_set_bit(irq_nr, ppc_lost_interrupts)) { 77 atomic_inc(&ppc_n_lost_interrupts); 78 set_dec(1); 79 } 80} 81 82static void pmac_mask_and_ack_irq(unsigned int virq) 83{ 84 unsigned int src = irq_map[virq].hwirq; 85 unsigned long bit = 1UL << (src & 0x1f); 86 int i = src >> 5; 87 unsigned long flags; 88 89 spin_lock_irqsave(&pmac_pic_lock, flags); 90 __clear_bit(src, ppc_cached_irq_mask); 91 if (__test_and_clear_bit(src, ppc_lost_interrupts)) 92 atomic_dec(&ppc_n_lost_interrupts); 93 out_le32(&pmac_irq_hw[i]->enable, ppc_cached_irq_mask[i]); 94 out_le32(&pmac_irq_hw[i]->ack, bit); 95 do { 96 /* make sure ack gets to controller before we enable 97 interrupts */ 98 mb(); 99 } while((in_le32(&pmac_irq_hw[i]->enable) & bit) 100 != (ppc_cached_irq_mask[i] & bit)); 101 spin_unlock_irqrestore(&pmac_pic_lock, flags); 102} 103 104static void pmac_ack_irq(unsigned int virq) 105{ 106 unsigned int src = irq_map[virq].hwirq; 107 unsigned long bit = 1UL << (src & 0x1f); 108 int i = src >> 5; 109 unsigned long flags; 110 111 spin_lock_irqsave(&pmac_pic_lock, flags); 112 if (__test_and_clear_bit(src, ppc_lost_interrupts)) 113 atomic_dec(&ppc_n_lost_interrupts); 114 out_le32(&pmac_irq_hw[i]->ack, bit); 115 (void)in_le32(&pmac_irq_hw[i]->ack); 116 spin_unlock_irqrestore(&pmac_pic_lock, flags); 117} 118 119static void __pmac_set_irq_mask(unsigned int irq_nr, int nokicklost) 120{ 121 unsigned long bit = 1UL << (irq_nr & 0x1f); 122 int i = irq_nr >> 5; 123 124 if ((unsigned)irq_nr >= max_irqs) 125 return; 126 127 /* enable unmasked interrupts */ 128 out_le32(&pmac_irq_hw[i]->enable, ppc_cached_irq_mask[i]); 129 130 do { 131 /* make sure mask gets to controller before we 132 return to user */ 133 mb(); 134 } while((in_le32(&pmac_irq_hw[i]->enable) & bit) 135 != (ppc_cached_irq_mask[i] & bit)); 136 137 /* 138 * Unfortunately, setting the bit in the enable register 139 * when the device interrupt is already on *doesn't* set 140 * the bit in the flag register or request another interrupt. 141 */ 142 if (bit & ppc_cached_irq_mask[i] & in_le32(&pmac_irq_hw[i]->level)) 143 __pmac_retrigger(irq_nr); 144} 145 146/* When an irq gets requested for the first client, if it's an 147 * edge interrupt, we clear any previous one on the controller 148 */ 149static unsigned int pmac_startup_irq(unsigned int virq) 150{ 151 unsigned long flags; 152 unsigned int src = irq_map[virq].hwirq; 153 unsigned long bit = 1UL << (src & 0x1f); 154 int i = src >> 5; 155 156 spin_lock_irqsave(&pmac_pic_lock, flags); 157 if ((irq_desc[virq].status & IRQ_LEVEL) == 0) 158 out_le32(&pmac_irq_hw[i]->ack, bit); 159 __set_bit(src, ppc_cached_irq_mask); 160 __pmac_set_irq_mask(src, 0); 161 spin_unlock_irqrestore(&pmac_pic_lock, flags); 162 163 return 0; 164} 165 166static void pmac_mask_irq(unsigned int virq) 167{ 168 unsigned long flags; 169 unsigned int src = irq_map[virq].hwirq; 170 171 spin_lock_irqsave(&pmac_pic_lock, flags); 172 __clear_bit(src, ppc_cached_irq_mask); 173 __pmac_set_irq_mask(src, 1); 174 spin_unlock_irqrestore(&pmac_pic_lock, flags); 175} 176 177static void pmac_unmask_irq(unsigned int virq) 178{ 179 unsigned long flags; 180 unsigned int src = irq_map[virq].hwirq; 181 182 spin_lock_irqsave(&pmac_pic_lock, flags); 183 __set_bit(src, ppc_cached_irq_mask); 184 __pmac_set_irq_mask(src, 0); 185 spin_unlock_irqrestore(&pmac_pic_lock, flags); 186} 187 188static int pmac_retrigger(unsigned int virq) 189{ 190 unsigned long flags; 191 192 spin_lock_irqsave(&pmac_pic_lock, flags); 193 __pmac_retrigger(irq_map[virq].hwirq); 194 spin_unlock_irqrestore(&pmac_pic_lock, flags); 195 return 1; 196} 197 198static struct irq_chip pmac_pic = { 199 .typename = " PMAC-PIC ", 200 .startup = pmac_startup_irq, 201 .mask = pmac_mask_irq, 202 .ack = pmac_ack_irq, 203 .mask_ack = pmac_mask_and_ack_irq, 204 .unmask = pmac_unmask_irq, 205 .retrigger = pmac_retrigger, 206}; 207 208static irqreturn_t gatwick_action(int cpl, void *dev_id) 209{ 210 unsigned long flags; 211 int irq, bits; 212 int rc = IRQ_NONE; 213 214 spin_lock_irqsave(&pmac_pic_lock, flags); 215 for (irq = max_irqs; (irq -= 32) >= max_real_irqs; ) { 216 int i = irq >> 5; 217 bits = in_le32(&pmac_irq_hw[i]->event) | ppc_lost_interrupts[i]; 218 /* We must read level interrupts from the level register */ 219 bits |= (in_le32(&pmac_irq_hw[i]->level) & level_mask[i]); 220 bits &= ppc_cached_irq_mask[i]; 221 if (bits == 0) 222 continue; 223 irq += __ilog2(bits); 224 spin_unlock_irqrestore(&pmac_pic_lock, flags); 225 __do_IRQ(irq); 226 spin_lock_irqsave(&pmac_pic_lock, flags); 227 rc = IRQ_HANDLED; 228 } 229 spin_unlock_irqrestore(&pmac_pic_lock, flags); 230 return rc; 231} 232 233static unsigned int pmac_pic_get_irq(void) 234{ 235 int irq; 236 unsigned long bits = 0; 237 unsigned long flags; 238 239#ifdef CONFIG_SMP 240 void psurge_smp_message_recv(void); 241 242 /* IPI's are a hack on the powersurge -- Cort */ 243 if ( smp_processor_id() != 0 ) { 244 psurge_smp_message_recv(); 245 return NO_IRQ_IGNORE; /* ignore, already handled */ 246 } 247#endif /* CONFIG_SMP */ 248 spin_lock_irqsave(&pmac_pic_lock, flags); 249 for (irq = max_real_irqs; (irq -= 32) >= 0; ) { 250 int i = irq >> 5; 251 bits = in_le32(&pmac_irq_hw[i]->event) | ppc_lost_interrupts[i]; 252 /* We must read level interrupts from the level register */ 253 bits |= (in_le32(&pmac_irq_hw[i]->level) & level_mask[i]); 254 bits &= ppc_cached_irq_mask[i]; 255 if (bits == 0) 256 continue; 257 irq += __ilog2(bits); 258 break; 259 } 260 spin_unlock_irqrestore(&pmac_pic_lock, flags); 261 if (unlikely(irq < 0)) 262 return NO_IRQ; 263 return irq_linear_revmap(pmac_pic_host, irq); 264} 265 266#ifdef CONFIG_XMON 267static struct irqaction xmon_action = { 268 .handler = xmon_irq, 269 .flags = 0, 270 .mask = CPU_MASK_NONE, 271 .name = "NMI - XMON" 272}; 273#endif 274 275static struct irqaction gatwick_cascade_action = { 276 .handler = gatwick_action, 277 .flags = IRQF_DISABLED, 278 .mask = CPU_MASK_NONE, 279 .name = "cascade", 280}; 281 282static int pmac_pic_host_match(struct irq_host *h, struct device_node *node) 283{ 284 /* We match all, we don't always have a node anyway */ 285 return 1; 286} 287 288static int pmac_pic_host_map(struct irq_host *h, unsigned int virq, 289 irq_hw_number_t hw) 290{ 291 struct irq_desc *desc = get_irq_desc(virq); 292 int level; 293 294 if (hw >= max_irqs) 295 return -EINVAL; 296 297 /* Mark level interrupts, set delayed disable for edge ones and set 298 * handlers 299 */ 300 level = !!(level_mask[hw >> 5] & (1UL << (hw & 0x1f))); 301 if (level) 302 desc->status |= IRQ_LEVEL; 303 set_irq_chip_and_handler(virq, &pmac_pic, level ? 304 handle_level_irq : handle_edge_irq); 305 return 0; 306} 307 308static int pmac_pic_host_xlate(struct irq_host *h, struct device_node *ct, 309 u32 *intspec, unsigned int intsize, 310 irq_hw_number_t *out_hwirq, 311 unsigned int *out_flags) 312 313{ 314 *out_flags = IRQ_TYPE_NONE; 315 *out_hwirq = *intspec; 316 return 0; 317} 318 319static struct irq_host_ops pmac_pic_host_ops = { 320 .match = pmac_pic_host_match, 321 .map = pmac_pic_host_map, 322 .xlate = pmac_pic_host_xlate, 323}; 324 325static void __init pmac_pic_probe_oldstyle(void) 326{ 327 int i; 328 struct device_node *master = NULL; 329 struct device_node *slave = NULL; 330 u8 __iomem *addr; 331 struct resource r; 332 333 /* Set our get_irq function */ 334 ppc_md.get_irq = pmac_pic_get_irq; 335 336 /* 337 * Find the interrupt controller type & node 338 */ 339 340 if ((master = of_find_node_by_name(NULL, "gc")) != NULL) { 341 max_irqs = max_real_irqs = 32; 342 level_mask[0] = GC_LEVEL_MASK; 343 } else if ((master = of_find_node_by_name(NULL, "ohare")) != NULL) { 344 max_irqs = max_real_irqs = 32; 345 level_mask[0] = OHARE_LEVEL_MASK; 346 347 /* We might have a second cascaded ohare */ 348 slave = of_find_node_by_name(NULL, "pci106b,7"); 349 if (slave) { 350 max_irqs = 64; 351 level_mask[1] = OHARE_LEVEL_MASK; 352 } 353 } else if ((master = of_find_node_by_name(NULL, "mac-io")) != NULL) { 354 max_irqs = max_real_irqs = 64; 355 level_mask[0] = HEATHROW_LEVEL_MASK; 356 level_mask[1] = 0; 357 358 /* We might have a second cascaded heathrow */ 359 slave = of_find_node_by_name(master, "mac-io"); 360 361 /* Check ordering of master & slave */ 362 if (of_device_is_compatible(master, "gatwick")) { 363 struct device_node *tmp; 364 BUG_ON(slave == NULL); 365 tmp = master; 366 master = slave; 367 slave = tmp; 368 } 369 370 /* We found a slave */ 371 if (slave) { 372 max_irqs = 128; 373 level_mask[2] = HEATHROW_LEVEL_MASK; 374 level_mask[3] = 0; 375 } 376 } 377 BUG_ON(master == NULL); 378 379 /* 380 * Allocate an irq host 381 */ 382 pmac_pic_host = irq_alloc_host(IRQ_HOST_MAP_LINEAR, max_irqs, 383 &pmac_pic_host_ops, 384 max_irqs); 385 BUG_ON(pmac_pic_host == NULL); 386 irq_set_default_host(pmac_pic_host); 387 388 /* Get addresses of first controller if we have a node for it */ 389 BUG_ON(of_address_to_resource(master, 0, &r)); 390 391 /* Map interrupts of primary controller */ 392 addr = (u8 __iomem *) ioremap(r.start, 0x40); 393 i = 0; 394 pmac_irq_hw[i++] = (volatile struct pmac_irq_hw __iomem *) 395 (addr + 0x20); 396 if (max_real_irqs > 32) 397 pmac_irq_hw[i++] = (volatile struct pmac_irq_hw __iomem *) 398 (addr + 0x10); 399 of_node_put(master); 400 401 printk(KERN_INFO "irq: Found primary Apple PIC %s for %d irqs\n", 402 master->full_name, max_real_irqs); 403 404 /* Map interrupts of cascaded controller */ 405 if (slave && !of_address_to_resource(slave, 0, &r)) { 406 addr = (u8 __iomem *)ioremap(r.start, 0x40); 407 pmac_irq_hw[i++] = (volatile struct pmac_irq_hw __iomem *) 408 (addr + 0x20); 409 if (max_irqs > 64) 410 pmac_irq_hw[i++] = 411 (volatile struct pmac_irq_hw __iomem *) 412 (addr + 0x10); 413 pmac_irq_cascade = irq_of_parse_and_map(slave, 0); 414 415 printk(KERN_INFO "irq: Found slave Apple PIC %s for %d irqs" 416 " cascade: %d\n", slave->full_name, 417 max_irqs - max_real_irqs, pmac_irq_cascade); 418 } 419 of_node_put(slave); 420 421 /* Disable all interrupts in all controllers */ 422 for (i = 0; i * 32 < max_irqs; ++i) 423 out_le32(&pmac_irq_hw[i]->enable, 0); 424 425 /* Hookup cascade irq */ 426 if (slave && pmac_irq_cascade != NO_IRQ) 427 setup_irq(pmac_irq_cascade, &gatwick_cascade_action); 428 429 printk(KERN_INFO "irq: System has %d possible interrupts\n", max_irqs); 430#ifdef CONFIG_XMON 431 setup_irq(irq_create_mapping(NULL, 20), &xmon_action); 432#endif 433} 434#endif /* CONFIG_PPC32 */ 435 436static void pmac_u3_cascade(unsigned int irq, struct irq_desc *desc) 437{ 438 struct mpic *mpic = desc->handler_data; 439 440 unsigned int cascade_irq = mpic_get_one_irq(mpic); 441 if (cascade_irq != NO_IRQ) 442 generic_handle_irq(cascade_irq); 443 desc->chip->eoi(irq); 444} 445 446static void __init pmac_pic_setup_mpic_nmi(struct mpic *mpic) 447{ 448#if defined(CONFIG_XMON) && defined(CONFIG_PPC32) 449 struct device_node* pswitch; 450 int nmi_irq; 451 452 pswitch = of_find_node_by_name(NULL, "programmer-switch"); 453 if (pswitch) { 454 nmi_irq = irq_of_parse_and_map(pswitch, 0); 455 if (nmi_irq != NO_IRQ) { 456 mpic_irq_set_priority(nmi_irq, 9); 457 setup_irq(nmi_irq, &xmon_action); 458 } 459 of_node_put(pswitch); 460 } 461#endif /* defined(CONFIG_XMON) && defined(CONFIG_PPC32) */ 462} 463 464static struct mpic * __init pmac_setup_one_mpic(struct device_node *np, 465 int master) 466{ 467 const char *name = master ? " MPIC 1 " : " MPIC 2 "; 468 struct resource r; 469 struct mpic *mpic; 470 unsigned int flags = master ? MPIC_PRIMARY : 0; 471 int rc; 472 473 rc = of_address_to_resource(np, 0, &r); 474 if (rc) 475 return NULL; 476 477 pmac_call_feature(PMAC_FTR_ENABLE_MPIC, np, 0, 0); 478 479 flags |= MPIC_WANTS_RESET; 480 if (of_get_property(np, "big-endian", NULL)) 481 flags |= MPIC_BIG_ENDIAN; 482 483 /* Primary Big Endian means HT interrupts. This is quite dodgy 484 * but works until I find a better way 485 */ 486 if (master && (flags & MPIC_BIG_ENDIAN)) 487 flags |= MPIC_U3_HT_IRQS; 488 489 mpic = mpic_alloc(np, r.start, flags, 0, 0, name); 490 if (mpic == NULL) 491 return NULL; 492 493 mpic_init(mpic); 494 495 return mpic; 496 } 497 498static int __init pmac_pic_probe_mpic(void) 499{ 500 struct mpic *mpic1, *mpic2; 501 struct device_node *np, *master = NULL, *slave = NULL; 502 unsigned int cascade; 503 504 /* We can have up to 2 MPICs cascaded */ 505 for (np = NULL; (np = of_find_node_by_type(np, "open-pic")) 506 != NULL;) { 507 if (master == NULL && 508 of_get_property(np, "interrupts", NULL) == NULL) 509 master = of_node_get(np); 510 else if (slave == NULL) 511 slave = of_node_get(np); 512 if (master && slave) 513 break; 514 } 515 516 /* Check for bogus setups */ 517 if (master == NULL && slave != NULL) { 518 master = slave; 519 slave = NULL; 520 } 521 522 /* Not found, default to good old pmac pic */ 523 if (master == NULL) 524 return -ENODEV; 525 526 /* Set master handler */ 527 ppc_md.get_irq = mpic_get_irq; 528 529 /* Setup master */ 530 mpic1 = pmac_setup_one_mpic(master, 1); 531 BUG_ON(mpic1 == NULL); 532 533 /* Install NMI if any */ 534 pmac_pic_setup_mpic_nmi(mpic1); 535 536 of_node_put(master); 537 538 /* No slave, let's go out */ 539 if (slave == NULL) 540 return 0; 541 542 /* Get/Map slave interrupt */ 543 cascade = irq_of_parse_and_map(slave, 0); 544 if (cascade == NO_IRQ) { 545 printk(KERN_ERR "Failed to map cascade IRQ\n"); 546 return 0; 547 } 548 549 mpic2 = pmac_setup_one_mpic(slave, 0); 550 if (mpic2 == NULL) { 551 printk(KERN_ERR "Failed to setup slave MPIC\n"); 552 of_node_put(slave); 553 return 0; 554 } 555 set_irq_data(cascade, mpic2); 556 set_irq_chained_handler(cascade, pmac_u3_cascade); 557 558 of_node_put(slave); 559 return 0; 560} 561 562 563void __init pmac_pic_init(void) 564{ 565 unsigned int flags = 0; 566 567 /* We configure the OF parsing based on our oldworld vs. newworld 568 * platform type and wether we were booted by BootX. 569 */ 570#ifdef CONFIG_PPC32 571 if (!pmac_newworld) 572 flags |= OF_IMAP_OLDWORLD_MAC; 573 if (of_get_property(of_chosen, "linux,bootx", NULL) != NULL) 574 flags |= OF_IMAP_NO_PHANDLE; 575#endif /* CONFIG_PPC_32 */ 576 577 of_irq_map_init(flags); 578 579 /* We first try to detect Apple's new Core99 chipset, since mac-io 580 * is quite different on those machines and contains an IBM MPIC2. 581 */ 582 if (pmac_pic_probe_mpic() == 0) 583 return; 584 585#ifdef CONFIG_PPC32 586 pmac_pic_probe_oldstyle(); 587#endif 588} 589 590#if defined(CONFIG_PM) && defined(CONFIG_PPC32) 591/* 592 * These procedures are used in implementing sleep on the powerbooks. 593 * sleep_save_intrs() saves the states of all interrupt enables 594 * and disables all interrupts except for the nominated one. 595 * sleep_restore_intrs() restores the states of all interrupt enables. 596 */ 597unsigned long sleep_save_mask[2]; 598 599/* This used to be passed by the PMU driver but that link got 600 * broken with the new driver model. We use this tweak for now... 601 * We really want to do things differently though... 602 */ 603static int pmacpic_find_viaint(void) 604{ 605 int viaint = -1; 606 607#ifdef CONFIG_ADB_PMU 608 struct device_node *np; 609 610 if (pmu_get_model() != PMU_OHARE_BASED) 611 goto not_found; 612 np = of_find_node_by_name(NULL, "via-pmu"); 613 if (np == NULL) 614 goto not_found; 615 viaint = irq_of_parse_and_map(np, 0);; 616#endif /* CONFIG_ADB_PMU */ 617 618not_found: 619 return viaint; 620} 621 622static int pmacpic_suspend(struct sys_device *sysdev, pm_message_t state) 623{ 624 int viaint = pmacpic_find_viaint(); 625 626 sleep_save_mask[0] = ppc_cached_irq_mask[0]; 627 sleep_save_mask[1] = ppc_cached_irq_mask[1]; 628 ppc_cached_irq_mask[0] = 0; 629 ppc_cached_irq_mask[1] = 0; 630 if (viaint > 0) 631 set_bit(viaint, ppc_cached_irq_mask); 632 out_le32(&pmac_irq_hw[0]->enable, ppc_cached_irq_mask[0]); 633 if (max_real_irqs > 32) 634 out_le32(&pmac_irq_hw[1]->enable, ppc_cached_irq_mask[1]); 635 (void)in_le32(&pmac_irq_hw[0]->event); 636 /* make sure mask gets to controller before we return to caller */ 637 mb(); 638 (void)in_le32(&pmac_irq_hw[0]->enable); 639 640 return 0; 641} 642 643static int pmacpic_resume(struct sys_device *sysdev) 644{ 645 int i; 646 647 out_le32(&pmac_irq_hw[0]->enable, 0); 648 if (max_real_irqs > 32) 649 out_le32(&pmac_irq_hw[1]->enable, 0); 650 mb(); 651 for (i = 0; i < max_real_irqs; ++i) 652 if (test_bit(i, sleep_save_mask)) 653 pmac_unmask_irq(i); 654 655 return 0; 656} 657 658#endif /* CONFIG_PM && CONFIG_PPC32 */ 659 660static struct sysdev_class pmacpic_sysclass = { 661 set_kset_name("pmac_pic"), 662}; 663 664static struct sys_device device_pmacpic = { 665 .id = 0, 666 .cls = &pmacpic_sysclass, 667}; 668 669static struct sysdev_driver driver_pmacpic = { 670#if defined(CONFIG_PM) && defined(CONFIG_PPC32) 671 .suspend = &pmacpic_suspend, 672 .resume = &pmacpic_resume, 673#endif /* CONFIG_PM && CONFIG_PPC32 */ 674}; 675 676static int __init init_pmacpic_sysfs(void) 677{ 678#ifdef CONFIG_PPC32 679 if (max_irqs == 0) 680 return -ENODEV; 681#endif 682 printk(KERN_DEBUG "Registering pmac pic with sysfs...\n"); 683 sysdev_class_register(&pmacpic_sysclass); 684 sysdev_register(&device_pmacpic); 685 sysdev_driver_register(&pmacpic_sysclass, &driver_pmacpic); 686 return 0; 687} 688 689subsys_initcall(init_pmacpic_sysfs); 690