1/*
2 * Platform information definitions.
3 *
4 * Copied from arch/ppc/syslib/cpm2_pic.c with minor subsequent updates
5 * to make in work in arch/powerpc/. Original (c) belongs to Dan Malek.
6 *
7 * Author:  Vitaly Bordug <vbordug@ru.mvista.com>
8 *
9 * 1999-2001 (c) Dan Malek <dan@embeddedalley.com>
10 * 2006 (c) MontaVista Software, Inc.
11 *
12 * This file is licensed under the terms of the GNU General Public License
13 * version 2. This program is licensed "as is" without any warranty of any
14 * kind, whether express or implied.
15 */
16
17/* The CPM2 internal interrupt controller.  It is usually
18 * the only interrupt controller.
19 * There are two 32-bit registers (high/low) for up to 64
20 * possible interrupts.
21 *
22 * Now, the fun starts.....Interrupt Numbers DO NOT MAP
23 * in a simple arithmetic fashion to mask or pending registers.
24 * That is, interrupt 4 does not map to bit position 4.
25 * We create two tables, indexed by vector number, to indicate
26 * which register to use and which bit in the register to use.
27 */
28
29#include <linux/stddef.h>
30#include <linux/init.h>
31#include <linux/sched.h>
32#include <linux/signal.h>
33#include <linux/irq.h>
34
35#include <asm/immap_cpm2.h>
36#include <asm/mpc8260.h>
37#include <asm/io.h>
38#include <asm/prom.h>
39#include <asm/fs_pd.h>
40
41#include "cpm2_pic.h"
42
43/* External IRQS */
44#define CPM2_IRQ_EXT1		19
45#define CPM2_IRQ_EXT7		25
46
47/* Port C IRQS */
48#define CPM2_IRQ_PORTC15	48
49#define CPM2_IRQ_PORTC0		63
50
51static intctl_cpm2_t *cpm2_intctl;
52
53static struct device_node *cpm2_pic_node;
54static struct irq_host *cpm2_pic_host;
55#define NR_MASK_WORDS   ((NR_IRQS + 31) / 32)
56static unsigned long ppc_cached_irq_mask[NR_MASK_WORDS];
57
58static const u_char irq_to_siureg[] = {
59	1, 1, 1, 1, 1, 1, 1, 1,
60	1, 1, 1, 1, 1, 1, 1, 1,
61	0, 0, 0, 0, 0, 0, 0, 0,
62	0, 0, 0, 0, 0, 0, 0, 0,
63	1, 1, 1, 1, 1, 1, 1, 1,
64	1, 1, 1, 1, 1, 1, 1, 1,
65	0, 0, 0, 0, 0, 0, 0, 0,
66	0, 0, 0, 0, 0, 0, 0, 0
67};
68
69/* bit numbers do not match the docs, these are precomputed so the bit for
70 * a given irq is (1 << irq_to_siubit[irq]) */
71static const u_char irq_to_siubit[] = {
72	 0, 15, 14, 13, 12, 11, 10,  9,
73	 8,  7,  6,  5,  4,  3,  2,  1,
74	 2,  1,  0, 14, 13, 12, 11, 10,
75	 9,  8,  7,  6,  5,  4,  3,  0,
76	31, 30, 29, 28, 27, 26, 25, 24,
77	23, 22, 21, 20, 19, 18, 17, 16,
78	16, 17, 18, 19, 20, 21, 22, 23,
79	24, 25, 26, 27, 28, 29, 30, 31,
80};
81
82static void cpm2_mask_irq(unsigned int virq)
83{
84	int	bit, word;
85	unsigned int irq_nr = virq_to_hw(virq);
86
87	bit = irq_to_siubit[irq_nr];
88	word = irq_to_siureg[irq_nr];
89
90	ppc_cached_irq_mask[word] &= ~(1 << bit);
91	out_be32(&cpm2_intctl->ic_simrh + word, ppc_cached_irq_mask[word]);
92}
93
94static void cpm2_unmask_irq(unsigned int virq)
95{
96	int	bit, word;
97	unsigned int irq_nr = virq_to_hw(virq);
98
99	bit = irq_to_siubit[irq_nr];
100	word = irq_to_siureg[irq_nr];
101
102	ppc_cached_irq_mask[word] |= 1 << bit;
103	out_be32(&cpm2_intctl->ic_simrh + word, ppc_cached_irq_mask[word]);
104}
105
106static void cpm2_ack(unsigned int virq)
107{
108	int	bit, word;
109	unsigned int irq_nr = virq_to_hw(virq);
110
111	bit = irq_to_siubit[irq_nr];
112	word = irq_to_siureg[irq_nr];
113
114	out_be32(&cpm2_intctl->ic_sipnrh + word, 1 << bit);
115}
116
117static void cpm2_end_irq(unsigned int virq)
118{
119	int	bit, word;
120	unsigned int irq_nr = virq_to_hw(virq);
121
122	if (!(irq_desc[irq_nr].status & (IRQ_DISABLED|IRQ_INPROGRESS))
123			&& irq_desc[irq_nr].action) {
124
125		bit = irq_to_siubit[irq_nr];
126		word = irq_to_siureg[irq_nr];
127
128		ppc_cached_irq_mask[word] |= 1 << bit;
129		out_be32(&cpm2_intctl->ic_simrh + word, ppc_cached_irq_mask[word]);
130
131		mb();
132	}
133}
134
135static int cpm2_set_irq_type(unsigned int virq, unsigned int flow_type)
136{
137	unsigned int src = virq_to_hw(virq);
138	struct irq_desc *desc = get_irq_desc(virq);
139	unsigned int vold, vnew, edibit;
140
141	if (flow_type == IRQ_TYPE_NONE)
142		flow_type = IRQ_TYPE_LEVEL_LOW;
143
144	if (flow_type & IRQ_TYPE_EDGE_RISING) {
145		printk(KERN_ERR "CPM2 PIC: sense type 0x%x not supported\n",
146			flow_type);
147		return -EINVAL;
148	}
149
150	desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL);
151	desc->status |= flow_type & IRQ_TYPE_SENSE_MASK;
152	if (flow_type & IRQ_TYPE_LEVEL_LOW)  {
153		desc->status |= IRQ_LEVEL;
154		desc->handle_irq = handle_level_irq;
155	} else
156		desc->handle_irq = handle_edge_irq;
157
158	/* internal IRQ senses are LEVEL_LOW
159	 * EXT IRQ and Port C IRQ senses are programmable
160	 */
161	if (src >= CPM2_IRQ_EXT1 && src <= CPM2_IRQ_EXT7)
162			edibit = (14 - (src - CPM2_IRQ_EXT1));
163	else
164		if (src >= CPM2_IRQ_PORTC15 && src <= CPM2_IRQ_PORTC0)
165			edibit = (31 - (src - CPM2_IRQ_PORTC15));
166		else
167			return (flow_type & IRQ_TYPE_LEVEL_LOW) ? 0 : -EINVAL;
168
169	vold = in_be32(&cpm2_intctl->ic_siexr);
170
171	if ((flow_type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_FALLING)
172		vnew = vold | (1 << edibit);
173	else
174		vnew = vold & ~(1 << edibit);
175
176	if (vold != vnew)
177		out_be32(&cpm2_intctl->ic_siexr, vnew);
178	return 0;
179}
180
181static struct irq_chip cpm2_pic = {
182	.typename = " CPM2 SIU ",
183	.mask = cpm2_mask_irq,
184	.unmask = cpm2_unmask_irq,
185	.ack = cpm2_ack,
186	.eoi = cpm2_end_irq,
187	.set_type = cpm2_set_irq_type,
188};
189
190unsigned int cpm2_get_irq(void)
191{
192	int irq;
193	unsigned long bits;
194
195       /* For CPM2, read the SIVEC register and shift the bits down
196         * to get the irq number.         */
197        bits = in_be32(&cpm2_intctl->ic_sivec);
198        irq = bits >> 26;
199
200	if (irq == 0)
201		return(-1);
202	return irq_linear_revmap(cpm2_pic_host, irq);
203}
204
205static int cpm2_pic_host_match(struct irq_host *h, struct device_node *node)
206{
207	return cpm2_pic_node == node;
208}
209
210static int cpm2_pic_host_map(struct irq_host *h, unsigned int virq,
211			  irq_hw_number_t hw)
212{
213	pr_debug("cpm2_pic_host_map(%d, 0x%lx)\n", virq, hw);
214
215	get_irq_desc(virq)->status |= IRQ_LEVEL;
216	set_irq_chip_and_handler(virq, &cpm2_pic, handle_level_irq);
217	return 0;
218}
219
220static int cpm2_pic_host_xlate(struct irq_host *h, struct device_node *ct,
221			    u32 *intspec, unsigned int intsize,
222			    irq_hw_number_t *out_hwirq, unsigned int *out_flags)
223{
224	*out_hwirq = intspec[0];
225	if (intsize > 1)
226		*out_flags = intspec[1];
227	else
228		*out_flags = IRQ_TYPE_NONE;
229	return 0;
230}
231
232static struct irq_host_ops cpm2_pic_host_ops = {
233	.match = cpm2_pic_host_match,
234	.map = cpm2_pic_host_map,
235	.xlate = cpm2_pic_host_xlate,
236};
237
238void cpm2_pic_init(struct device_node *node)
239{
240	int i;
241
242	cpm2_intctl = cpm2_map(im_intctl);
243
244	/* Clear the CPM IRQ controller, in case it has any bits set
245	 * from the bootloader
246	 */
247
248	/* Mask out everything */
249
250	out_be32(&cpm2_intctl->ic_simrh, 0x00000000);
251	out_be32(&cpm2_intctl->ic_simrl, 0x00000000);
252
253	wmb();
254
255	/* Ack everything */
256	out_be32(&cpm2_intctl->ic_sipnrh, 0xffffffff);
257	out_be32(&cpm2_intctl->ic_sipnrl, 0xffffffff);
258	wmb();
259
260	/* Dummy read of the vector */
261	i = in_be32(&cpm2_intctl->ic_sivec);
262	rmb();
263
264	/* Initialize the default interrupt mapping priorities,
265	 * in case the boot rom changed something on us.
266	 */
267	out_be16(&cpm2_intctl->ic_sicr, 0);
268	out_be32(&cpm2_intctl->ic_scprrh, 0x05309770);
269	out_be32(&cpm2_intctl->ic_scprrl, 0x05309770);
270
271	/* create a legacy host */
272	cpm2_pic_node = of_node_get(node);
273	cpm2_pic_host = irq_alloc_host(IRQ_HOST_MAP_LINEAR, 64, &cpm2_pic_host_ops, 64);
274	if (cpm2_pic_host == NULL) {
275		printk(KERN_ERR "CPM2 PIC: failed to allocate irq host!\n");
276		return;
277	}
278}
279