1/* The CPM2 internal interrupt controller. It is usually 2 * the only interrupt controller. 3 * There are two 32-bit registers (high/low) for up to 64 4 * possible interrupts. 5 * 6 * Now, the fun starts.....Interrupt Numbers DO NOT MAP 7 * in a simple arithmetic fashion to mask or pending registers. 8 * That is, interrupt 4 does not map to bit position 4. 9 * We create two tables, indexed by vector number, to indicate 10 * which register to use and which bit in the register to use. 11 */ 12 13#include <linux/stddef.h> 14#include <linux/init.h> 15#include <linux/sched.h> 16#include <linux/signal.h> 17#include <linux/irq.h> 18 19#include <asm/immap_cpm2.h> 20#include <asm/mpc8260.h> 21 22#include "cpm2_pic.h" 23 24static u_char irq_to_siureg[] = { 25 1, 1, 1, 1, 1, 1, 1, 1, 26 1, 1, 1, 1, 1, 1, 1, 1, 27 0, 0, 0, 0, 0, 0, 0, 0, 28 0, 0, 0, 0, 0, 0, 0, 0, 29 1, 1, 1, 1, 1, 1, 1, 1, 30 1, 1, 1, 1, 1, 1, 1, 1, 31 0, 0, 0, 0, 0, 0, 0, 0, 32 0, 0, 0, 0, 0, 0, 0, 0 33}; 34 35/* bit numbers do not match the docs, these are precomputed so the bit for 36 * a given irq is (1 << irq_to_siubit[irq]) */ 37static u_char irq_to_siubit[] = { 38 0, 15, 14, 13, 12, 11, 10, 9, 39 8, 7, 6, 5, 4, 3, 2, 1, 40 2, 1, 0, 14, 13, 12, 11, 10, 41 9, 8, 7, 6, 5, 4, 3, 0, 42 31, 30, 29, 28, 27, 26, 25, 24, 43 23, 22, 21, 20, 19, 18, 17, 16, 44 16, 17, 18, 19, 20, 21, 22, 23, 45 24, 25, 26, 27, 28, 29, 30, 31, 46}; 47 48static void cpm2_mask_irq(unsigned int irq_nr) 49{ 50 int bit, word; 51 volatile uint *simr; 52 53 irq_nr -= CPM_IRQ_OFFSET; 54 55 bit = irq_to_siubit[irq_nr]; 56 word = irq_to_siureg[irq_nr]; 57 58 simr = &(cpm2_immr->im_intctl.ic_simrh); 59 ppc_cached_irq_mask[word] &= ~(1 << bit); 60 simr[word] = ppc_cached_irq_mask[word]; 61} 62 63static void cpm2_unmask_irq(unsigned int irq_nr) 64{ 65 int bit, word; 66 volatile uint *simr; 67 68 irq_nr -= CPM_IRQ_OFFSET; 69 70 bit = irq_to_siubit[irq_nr]; 71 word = irq_to_siureg[irq_nr]; 72 73 simr = &(cpm2_immr->im_intctl.ic_simrh); 74 ppc_cached_irq_mask[word] |= 1 << bit; 75 simr[word] = ppc_cached_irq_mask[word]; 76} 77 78static void cpm2_mask_and_ack(unsigned int irq_nr) 79{ 80 int bit, word; 81 volatile uint *simr, *sipnr; 82 83 irq_nr -= CPM_IRQ_OFFSET; 84 85 bit = irq_to_siubit[irq_nr]; 86 word = irq_to_siureg[irq_nr]; 87 88 simr = &(cpm2_immr->im_intctl.ic_simrh); 89 sipnr = &(cpm2_immr->im_intctl.ic_sipnrh); 90 ppc_cached_irq_mask[word] &= ~(1 << bit); 91 simr[word] = ppc_cached_irq_mask[word]; 92 sipnr[word] = 1 << bit; 93} 94 95static void cpm2_end_irq(unsigned int irq_nr) 96{ 97 int bit, word; 98 volatile uint *simr; 99 100 if (!(irq_desc[irq_nr].status & (IRQ_DISABLED|IRQ_INPROGRESS)) 101 && irq_desc[irq_nr].action) { 102 103 irq_nr -= CPM_IRQ_OFFSET; 104 bit = irq_to_siubit[irq_nr]; 105 word = irq_to_siureg[irq_nr]; 106 107 simr = &(cpm2_immr->im_intctl.ic_simrh); 108 ppc_cached_irq_mask[word] |= 1 << bit; 109 simr[word] = ppc_cached_irq_mask[word]; 110 mb(); 111 } 112} 113 114static struct hw_interrupt_type cpm2_pic = { 115 .typename = " CPM2 SIU ", 116 .enable = cpm2_unmask_irq, 117 .disable = cpm2_mask_irq, 118 .ack = cpm2_mask_and_ack, 119 .end = cpm2_end_irq, 120}; 121 122int cpm2_get_irq(void) 123{ 124 int irq; 125 unsigned long bits; 126 127 /* For CPM2, read the SIVEC register and shift the bits down 128 * to get the irq number. */ 129 bits = cpm2_immr->im_intctl.ic_sivec; 130 irq = bits >> 26; 131 132 if (irq == 0) 133 return(-1); 134 return irq+CPM_IRQ_OFFSET; 135} 136 137void cpm2_init_IRQ(void) 138{ 139 int i; 140 141 /* Clear the CPM IRQ controller, in case it has any bits set 142 * from the bootloader 143 */ 144 145 /* Mask out everything */ 146 cpm2_immr->im_intctl.ic_simrh = 0x00000000; 147 cpm2_immr->im_intctl.ic_simrl = 0x00000000; 148 wmb(); 149 150 /* Ack everything */ 151 cpm2_immr->im_intctl.ic_sipnrh = 0xffffffff; 152 cpm2_immr->im_intctl.ic_sipnrl = 0xffffffff; 153 wmb(); 154 155 /* Dummy read of the vector */ 156 i = cpm2_immr->im_intctl.ic_sivec; 157 rmb(); 158 159 /* Initialize the default interrupt mapping priorities, 160 * in case the boot rom changed something on us. 161 */ 162 cpm2_immr->im_intctl.ic_sicr = 0; 163 cpm2_immr->im_intctl.ic_scprrh = 0x05309770; 164 cpm2_immr->im_intctl.ic_scprrl = 0x05309770; 165 166 167 /* Enable chaining to OpenPIC, and make everything level 168 */ 169 for (i = 0; i < NR_CPM_INTS; i++) { 170 irq_desc[i+CPM_IRQ_OFFSET].chip = &cpm2_pic; 171 irq_desc[i+CPM_IRQ_OFFSET].status |= IRQ_LEVEL; 172 } 173} 174