Searched refs:mmio (Results 1 - 25 of 30) sorted by relevance

12

/freebsd-11-stable/sys/mips/rmi/
H A Dpic.h162 xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET); local
166 reg = xlr_read_reg(mmio, PIC_CTRL);
174 xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET); local
177 xlr_write_reg(mmio, PIC_CTRL, control);
184 xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET); local
187 xlr_write_reg(mmio, PIC_CTRL, (control | xlr_read_reg(mmio, PIC_CTRL)));
194 xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET); local
196 xlr_write_reg(mmio, PIC_INT_ACK, 1U << picintr);
202 xlr_reg_t *mmio local
213 xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET); local
225 xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET); local
238 xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET); local
249 xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET); local
261 xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET); local
[all...]
H A Dxlr_machdep.c307 xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET); local
312 xlr_write_reg(mmio, PIC_CTRL, 0);
322 xlr_write_reg(mmio, PIC_IRT_1(i), (1 << 30) | (1 << 6) | irq);
324 xlr_write_reg(mmio, PIC_IRT_0(i), 0x01);
522 xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_GPIO_OFFSET); local
525 xlr_write_reg(mmio, 8, 1);
H A Diodi.c89 xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_FLASH_OFFSET); local
91 xlr_write_reg(mmio, 0x60, 0xffffffff);
H A Dboard.c62 xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_GPIO_OFFSET); local
65 resetconf = xlr_read_reg(mmio, 21);
276 xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_GPIO_OFFSET); local
281 tmp = xlr_read_reg(mmio, 35);
/freebsd-11-stable/sys/dev/drm/
H A Dsis_drv.h57 #define SIS_BASE (dev_priv->mmio)
62 drm_local_map_t *mmio; member in struct:drm_sis_private
H A Dvia_map.c53 dev_priv->mmio = drm_core_findmap(dev, init->mmio_offset);
54 if (!dev_priv->mmio) {
55 DRM_ERROR("could not find mmio region!\n");
H A Dvia_drv.h68 drm_local_map_t *mmio; member in struct:drm_via_private
111 #define VIA_BASE ((dev_priv->mmio))
H A Dr128_drv.h122 drm_local_map_t *mmio; member in struct:drm_r128_private
396 #define R128_READ(reg) DRM_READ32( dev_priv->mmio, (reg) )
397 #define R128_WRITE(reg,val) DRM_WRITE32( dev_priv->mmio, (reg), (val) )
398 #define R128_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) )
399 #define R128_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) )
H A Dmga_drv.h116 * \sa drm_mga_private_t::mmio
145 drm_local_map_t *mmio; member in struct:drm_mga_private
203 #define MGA_BASE( reg ) ((unsigned long)(dev_priv->mmio->handle))
220 #define MGA_READ8( reg ) DRM_READ8(dev_priv->mmio, (reg))
221 #define MGA_READ( reg ) DRM_READ32(dev_priv->mmio, (reg))
222 #define MGA_WRITE8( reg, val ) DRM_WRITE8(dev_priv->mmio, (reg), (val))
223 #define MGA_WRITE( reg, val ) DRM_WRITE32(dev_priv->mmio, (reg), (val))
H A Dsavage_drv.h158 drm_local_map_t *mmio; member in struct:drm_savage_private
491 #define SAVAGE_READ(reg) DRM_READ32( dev_priv->mmio, (reg) )
492 #define SAVAGE_WRITE(reg) DRM_WRITE32( dev_priv->mmio, (reg) )
H A Dmach64_drv.h110 drm_local_map_t *mmio; member in struct:drm_mach64_private
494 #define MACH64_READ(reg) DRM_READ32(dev_priv->mmio, (reg) )
495 #define MACH64_WRITE(reg,val) DRM_WRITE32(dev_priv->mmio, (reg), (val) )
H A Dmga_dma.c724 _DRM_REGISTERS, _DRM_READ_ONLY, & dev_priv->mmio);
852 dev_priv->mmio = drm_core_findmap(dev, init->mmio_offset);
853 if (!dev_priv->mmio) {
854 DRM_ERROR("failed to find mmio region!\n");
996 dev_priv->mmio = NULL;
H A Dradeon_cp.c111 ret = DRM_READ32(dev_priv->mmio, addr);
113 DRM_WRITE32(dev_priv->mmio, RADEON_MM_INDEX, addr);
114 ret = DRM_READ32(dev_priv->mmio, RADEON_MM_DATA);
1721 if (dev_priv->mmio) /* remove this after permanent addmaps */
1724 if (dev_priv->mmio) { /* remove all surfaces */
2036 _DRM_READ_ONLY | _DRM_DRIVER, &dev_priv->mmio);
2084 drm_rmmap(dev, dev_priv->mmio);
H A Dradeon_drv.h375 drm_local_map_t *mmio; member in struct:drm_radeon_private
1825 #define RADEON_READ(reg) DRM_READ32( dev_priv->mmio, (reg) )
1829 DRM_WRITE32(dev_priv->mmio, (reg), (val)); \
1831 DRM_WRITE32(dev_priv->mmio, RADEON_MM_INDEX, (reg)); \
1832 DRM_WRITE32(dev_priv->mmio, RADEON_MM_DATA, (val)); \
1835 #define RADEON_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) )
1836 #define RADEON_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) )
H A Dr128_cce.c469 dev_priv->mmio = drm_core_findmap(dev, init->mmio_offset);
470 if (!dev_priv->mmio) {
471 DRM_ERROR("could not find mmio region!\n");
H A Dvia_dma.c188 if (!dev_priv || !dev_priv->mmio) {
232 (volatile uint32_t *)((char *)dev_priv->mmio->virtual +
H A Dsavage_bci.c639 _DRM_READ_ONLY, &dev_priv->mmio);
860 ((uint8_t *)dev_priv->mmio->virtual + SAVAGE_BCI_OFFSET);
/freebsd-11-stable/sys/dev/usb/controller/
H A Dehci_imx.c144 struct resource *mmio; member in struct:imx_usbmisc_softc
161 reg = bus_read_4(sc->mmio, index * sizeof(uint32_t));
162 bus_write_4(sc->mmio, index * sizeof(uint32_t), reg | bits);
173 reg = bus_read_4(sc->mmio, index * sizeof(uint32_t));
174 bus_write_4(sc->mmio, index * sizeof(uint32_t), reg & ~bits);
199 if (sc->mmio != NULL)
200 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mmio);
216 sc->mmio = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
218 if (sc->mmio == NULL) {
/freebsd-11-stable/sys/amd64/vmm/io/
H A Dppt.c89 struct pptseg mmio[MAX_MMIOSEGS]; member in struct:pptdev
224 seg = &ppt->mmio[i];
352 seg = &ppt->mmio[i];
458 seg = &ppt->mmio[i];
/freebsd-11-stable/sys/dev/drm2/i915/
H A Dintel_ringbuffer.c855 u32 mmio = 0; local
863 mmio = RENDER_HWS_PGA_GEN7;
866 mmio = BLT_HWS_PGA_GEN7;
869 mmio = BSD_HWS_PGA_GEN7;
873 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
875 mmio = RING_HWS_PGA(ring->mmio_base);
878 I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
879 POSTING_READ(mmio);
/freebsd-11-stable/sys/dev/beri/virtio/
H A Dvirtio_mmio_platform.c63 #include <dev/virtio/mmio/virtio_mmio.h>
H A Dvirtio_block.c68 #include <dev/virtio/mmio/virtio_mmio.h>
/freebsd-11-stable/sys/dev/drm2/radeon/
H A Dradeon_drv.h281 drm_local_map_t *mmio; member in struct:drm_radeon_private
1850 #define RADEON_READ(reg) DRM_READ32( dev_priv->mmio, (reg) )
1854 DRM_WRITE32(dev_priv->mmio, (reg), (val)); \
1856 DRM_WRITE32(dev_priv->mmio, RADEON_MM_INDEX, (reg)); \
1857 DRM_WRITE32(dev_priv->mmio, RADEON_MM_DATA, (val)); \
1860 #define RADEON_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) )
1861 #define RADEON_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) )
/freebsd-11-stable/sys/mips/rmi/dev/nlge/
H A Dif_nlge.c2186 xlr_reg_t *mmio; local
2203 mmio = sc->base;
2228 NLGE_WRITE(mmio, R_INTERFACE_CONTROL, sgmii_speed[sc->speed]);
2231 NLGE_WRITE(mmio, R_MAC_CONFIG_2, 0x7117);
2233 NLGE_WRITE(mmio, R_MAC_CONFIG_2, 0x7217);
2239 NLGE_WRITE(mmio, R_CORECONTROL, core_ctl[sc->speed]);
/freebsd-11-stable/sys/mips/rmi/dev/sec/
H A Drmilib.c107 xlr_reg_t *mmio; local
109 mmio = sc->mmio = xlr_io_mmio(XLR_IO_SECURITY_OFFSET);
110 xlr_write_reg(mmio, SEC_DMA_CREDIT, SEC_DMA_CREDIT_CONFIG);
111 xlr_write_reg(mmio, SEC_CONFIG2, SEC_CFG2_ROUND_ROBIN_ON);
114 xlr_write_reg(mmio,
121 xlr_write_reg(mmio,

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