1/* r128_drv.h -- Private header for r128 driver -*- linux-c -*- 2 * Created: Mon Dec 13 09:51:11 1999 by faith@precisioninsight.com 3 */ 4/*- 5 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. 6 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 7 * All rights reserved. 8 * 9 * Permission is hereby granted, free of charge, to any person obtaining a 10 * copy of this software and associated documentation files (the "Software"), 11 * to deal in the Software without restriction, including without limitation 12 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 13 * and/or sell copies of the Software, and to permit persons to whom the 14 * Software is furnished to do so, subject to the following conditions: 15 * 16 * The above copyright notice and this permission notice (including the next 17 * paragraph) shall be included in all copies or substantial portions of the 18 * Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 23 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 24 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 25 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 26 * DEALINGS IN THE SOFTWARE. 27 * 28 * Authors: 29 * Rickard E. (Rik) Faith <faith@valinux.com> 30 * Kevin E. Martin <martin@valinux.com> 31 * Gareth Hughes <gareth@valinux.com> 32 * Michel D�zer <daenzerm@student.ethz.ch> 33 */ 34 35#include <sys/cdefs.h> 36__FBSDID("$FreeBSD$"); 37 38#ifndef __R128_DRV_H__ 39#define __R128_DRV_H__ 40 41/* General customization: 42 */ 43#define DRIVER_AUTHOR "Gareth Hughes, VA Linux Systems Inc." 44 45#define DRIVER_NAME "r128" 46#define DRIVER_DESC "ATI Rage 128" 47#define DRIVER_DATE "20030725" 48 49/* Interface history: 50 * 51 * ?? - ?? 52 * 2.4 - Add support for ycbcr textures (no new ioctls) 53 * 2.5 - Add FLIP ioctl, disable FULLSCREEN. 54 */ 55#define DRIVER_MAJOR 2 56#define DRIVER_MINOR 5 57#define DRIVER_PATCHLEVEL 0 58 59#define GET_RING_HEAD(dev_priv) R128_READ( R128_PM4_BUFFER_DL_RPTR ) 60 61typedef struct drm_r128_freelist { 62 unsigned int age; 63 struct drm_buf *buf; 64 struct drm_r128_freelist *next; 65 struct drm_r128_freelist *prev; 66} drm_r128_freelist_t; 67 68typedef struct drm_r128_ring_buffer { 69 u32 *start; 70 u32 *end; 71 int size; 72 int size_l2qw; 73 74 u32 tail; 75 u32 tail_mask; 76 int space; 77 78 int high_mark; 79} drm_r128_ring_buffer_t; 80 81typedef struct drm_r128_private { 82 drm_r128_ring_buffer_t ring; 83 drm_r128_sarea_t *sarea_priv; 84 85 int cce_mode; 86 int cce_fifo_size; 87 int cce_running; 88 89 drm_r128_freelist_t *head; 90 drm_r128_freelist_t *tail; 91 92 int usec_timeout; 93 int is_pci; 94 unsigned long cce_buffers_offset; 95 96 atomic_t idle_count; 97 98 int page_flipping; 99 int current_page; 100 u32 crtc_offset; 101 u32 crtc_offset_cntl; 102 103 atomic_t vbl_received; 104 105 u32 color_fmt; 106 unsigned int front_offset; 107 unsigned int front_pitch; 108 unsigned int back_offset; 109 unsigned int back_pitch; 110 111 u32 depth_fmt; 112 unsigned int depth_offset; 113 unsigned int depth_pitch; 114 unsigned int span_offset; 115 116 u32 front_pitch_offset_c; 117 u32 back_pitch_offset_c; 118 u32 depth_pitch_offset_c; 119 u32 span_pitch_offset_c; 120 121 drm_local_map_t *sarea; 122 drm_local_map_t *mmio; 123 drm_local_map_t *cce_ring; 124 drm_local_map_t *ring_rptr; 125 drm_local_map_t *agp_textures; 126 struct drm_ati_pcigart_info gart_info; 127} drm_r128_private_t; 128 129typedef struct drm_r128_buf_priv { 130 u32 age; 131 int prim; 132 int discard; 133 int dispatched; 134 drm_r128_freelist_t *list_entry; 135} drm_r128_buf_priv_t; 136 137extern struct drm_ioctl_desc r128_ioctls[]; 138extern int r128_max_ioctl; 139 140 /* r128_cce.c */ 141extern int r128_cce_init(struct drm_device *dev, void *data, struct drm_file *file_priv); 142extern int r128_cce_start(struct drm_device *dev, void *data, struct drm_file *file_priv); 143extern int r128_cce_stop(struct drm_device *dev, void *data, struct drm_file *file_priv); 144extern int r128_cce_reset(struct drm_device *dev, void *data, struct drm_file *file_priv); 145extern int r128_cce_idle(struct drm_device *dev, void *data, struct drm_file *file_priv); 146extern int r128_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv); 147extern int r128_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv); 148extern int r128_cce_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv); 149 150extern void r128_freelist_reset(struct drm_device * dev); 151 152extern int r128_wait_ring(drm_r128_private_t * dev_priv, int n); 153 154extern int r128_do_cce_idle(drm_r128_private_t * dev_priv); 155extern int r128_do_cleanup_cce(struct drm_device * dev); 156 157extern int r128_enable_vblank(struct drm_device *dev, int crtc); 158extern void r128_disable_vblank(struct drm_device *dev, int crtc); 159extern u32 r128_get_vblank_counter(struct drm_device *dev, int crtc); 160extern irqreturn_t r128_driver_irq_handler(DRM_IRQ_ARGS); 161extern void r128_driver_irq_preinstall(struct drm_device * dev); 162extern int r128_driver_irq_postinstall(struct drm_device * dev); 163extern void r128_driver_irq_uninstall(struct drm_device * dev); 164extern void r128_driver_lastclose(struct drm_device * dev); 165extern int r128_driver_load(struct drm_device * dev, unsigned long flags); 166extern void r128_driver_preclose(struct drm_device * dev, 167 struct drm_file *file_priv); 168 169extern long r128_compat_ioctl(struct file *filp, unsigned int cmd, 170 unsigned long arg); 171 172/* Register definitions, register access macros and drmAddMap constants 173 * for Rage 128 kernel driver. 174 */ 175 176#define R128_AUX_SC_CNTL 0x1660 177# define R128_AUX1_SC_EN (1 << 0) 178# define R128_AUX1_SC_MODE_OR (0 << 1) 179# define R128_AUX1_SC_MODE_NAND (1 << 1) 180# define R128_AUX2_SC_EN (1 << 2) 181# define R128_AUX2_SC_MODE_OR (0 << 3) 182# define R128_AUX2_SC_MODE_NAND (1 << 3) 183# define R128_AUX3_SC_EN (1 << 4) 184# define R128_AUX3_SC_MODE_OR (0 << 5) 185# define R128_AUX3_SC_MODE_NAND (1 << 5) 186#define R128_AUX1_SC_LEFT 0x1664 187#define R128_AUX1_SC_RIGHT 0x1668 188#define R128_AUX1_SC_TOP 0x166c 189#define R128_AUX1_SC_BOTTOM 0x1670 190#define R128_AUX2_SC_LEFT 0x1674 191#define R128_AUX2_SC_RIGHT 0x1678 192#define R128_AUX2_SC_TOP 0x167c 193#define R128_AUX2_SC_BOTTOM 0x1680 194#define R128_AUX3_SC_LEFT 0x1684 195#define R128_AUX3_SC_RIGHT 0x1688 196#define R128_AUX3_SC_TOP 0x168c 197#define R128_AUX3_SC_BOTTOM 0x1690 198 199#define R128_BRUSH_DATA0 0x1480 200#define R128_BUS_CNTL 0x0030 201# define R128_BUS_MASTER_DIS (1 << 6) 202 203#define R128_CLOCK_CNTL_INDEX 0x0008 204#define R128_CLOCK_CNTL_DATA 0x000c 205# define R128_PLL_WR_EN (1 << 7) 206#define R128_CONSTANT_COLOR_C 0x1d34 207#define R128_CRTC_OFFSET 0x0224 208#define R128_CRTC_OFFSET_CNTL 0x0228 209# define R128_CRTC_OFFSET_FLIP_CNTL (1 << 16) 210 211#define R128_DP_GUI_MASTER_CNTL 0x146c 212# define R128_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0) 213# define R128_GMC_DST_PITCH_OFFSET_CNTL (1 << 1) 214# define R128_GMC_BRUSH_SOLID_COLOR (13 << 4) 215# define R128_GMC_BRUSH_NONE (15 << 4) 216# define R128_GMC_DST_16BPP (4 << 8) 217# define R128_GMC_DST_24BPP (5 << 8) 218# define R128_GMC_DST_32BPP (6 << 8) 219# define R128_GMC_DST_DATATYPE_SHIFT 8 220# define R128_GMC_SRC_DATATYPE_COLOR (3 << 12) 221# define R128_DP_SRC_SOURCE_MEMORY (2 << 24) 222# define R128_DP_SRC_SOURCE_HOST_DATA (3 << 24) 223# define R128_GMC_CLR_CMP_CNTL_DIS (1 << 28) 224# define R128_GMC_AUX_CLIP_DIS (1 << 29) 225# define R128_GMC_WR_MSK_DIS (1 << 30) 226# define R128_ROP3_S 0x00cc0000 227# define R128_ROP3_P 0x00f00000 228#define R128_DP_WRITE_MASK 0x16cc 229#define R128_DST_PITCH_OFFSET_C 0x1c80 230# define R128_DST_TILE (1U << 31) 231 232#define R128_GEN_INT_CNTL 0x0040 233# define R128_CRTC_VBLANK_INT_EN (1 << 0) 234#define R128_GEN_INT_STATUS 0x0044 235# define R128_CRTC_VBLANK_INT (1 << 0) 236# define R128_CRTC_VBLANK_INT_AK (1 << 0) 237#define R128_GEN_RESET_CNTL 0x00f0 238# define R128_SOFT_RESET_GUI (1 << 0) 239 240#define R128_GUI_SCRATCH_REG0 0x15e0 241#define R128_GUI_SCRATCH_REG1 0x15e4 242#define R128_GUI_SCRATCH_REG2 0x15e8 243#define R128_GUI_SCRATCH_REG3 0x15ec 244#define R128_GUI_SCRATCH_REG4 0x15f0 245#define R128_GUI_SCRATCH_REG5 0x15f4 246 247#define R128_GUI_STAT 0x1740 248# define R128_GUI_FIFOCNT_MASK 0x0fff 249# define R128_GUI_ACTIVE (1U << 31) 250 251#define R128_MCLK_CNTL 0x000f 252# define R128_FORCE_GCP (1 << 16) 253# define R128_FORCE_PIPE3D_CP (1 << 17) 254# define R128_FORCE_RCP (1 << 18) 255 256#define R128_PC_GUI_CTLSTAT 0x1748 257#define R128_PC_NGUI_CTLSTAT 0x0184 258# define R128_PC_FLUSH_GUI (3 << 0) 259# define R128_PC_RI_GUI (1 << 2) 260# define R128_PC_FLUSH_ALL 0x00ff 261# define R128_PC_BUSY (1U << 31) 262 263#define R128_PCI_GART_PAGE 0x017c 264#define R128_PRIM_TEX_CNTL_C 0x1cb0 265 266#define R128_SCALE_3D_CNTL 0x1a00 267#define R128_SEC_TEX_CNTL_C 0x1d00 268#define R128_SEC_TEXTURE_BORDER_COLOR_C 0x1d3c 269#define R128_SETUP_CNTL 0x1bc4 270#define R128_STEN_REF_MASK_C 0x1d40 271 272#define R128_TEX_CNTL_C 0x1c9c 273# define R128_TEX_CACHE_FLUSH (1 << 23) 274 275#define R128_WAIT_UNTIL 0x1720 276# define R128_EVENT_CRTC_OFFSET (1 << 0) 277#define R128_WINDOW_XY_OFFSET 0x1bcc 278 279/* CCE registers 280 */ 281#define R128_PM4_BUFFER_OFFSET 0x0700 282#define R128_PM4_BUFFER_CNTL 0x0704 283# define R128_PM4_MASK (15 << 28) 284# define R128_PM4_NONPM4 (0 << 28) 285# define R128_PM4_192PIO (1 << 28) 286# define R128_PM4_192BM (2 << 28) 287# define R128_PM4_128PIO_64INDBM (3 << 28) 288# define R128_PM4_128BM_64INDBM (4 << 28) 289# define R128_PM4_64PIO_128INDBM (5 << 28) 290# define R128_PM4_64BM_128INDBM (6 << 28) 291# define R128_PM4_64PIO_64VCBM_64INDBM (7 << 28) 292# define R128_PM4_64BM_64VCBM_64INDBM (8 << 28) 293# define R128_PM4_64PIO_64VCPIO_64INDPIO (15 << 28) 294# define R128_PM4_BUFFER_CNTL_NOUPDATE (1 << 27) 295 296#define R128_PM4_BUFFER_WM_CNTL 0x0708 297# define R128_WMA_SHIFT 0 298# define R128_WMB_SHIFT 8 299# define R128_WMC_SHIFT 16 300# define R128_WB_WM_SHIFT 24 301 302#define R128_PM4_BUFFER_DL_RPTR_ADDR 0x070c 303#define R128_PM4_BUFFER_DL_RPTR 0x0710 304#define R128_PM4_BUFFER_DL_WPTR 0x0714 305# define R128_PM4_BUFFER_DL_DONE (1U << 31) 306 307#define R128_PM4_VC_FPU_SETUP 0x071c 308 309#define R128_PM4_IW_INDOFF 0x0738 310#define R128_PM4_IW_INDSIZE 0x073c 311 312#define R128_PM4_STAT 0x07b8 313# define R128_PM4_FIFOCNT_MASK 0x0fff 314# define R128_PM4_BUSY (1 << 16) 315# define R128_PM4_GUI_ACTIVE (1U << 31) 316 317#define R128_PM4_MICROCODE_ADDR 0x07d4 318#define R128_PM4_MICROCODE_RADDR 0x07d8 319#define R128_PM4_MICROCODE_DATAH 0x07dc 320#define R128_PM4_MICROCODE_DATAL 0x07e0 321 322#define R128_PM4_BUFFER_ADDR 0x07f0 323#define R128_PM4_MICRO_CNTL 0x07fc 324# define R128_PM4_MICRO_FREERUN (1 << 30) 325 326#define R128_PM4_FIFO_DATA_EVEN 0x1000 327#define R128_PM4_FIFO_DATA_ODD 0x1004 328 329/* CCE command packets 330 */ 331#define R128_CCE_PACKET0 0x00000000 332#define R128_CCE_PACKET1 0x40000000 333#define R128_CCE_PACKET2 0x80000000 334#define R128_CCE_PACKET3 0xC0000000 335# define R128_CNTL_HOSTDATA_BLT 0x00009400 336# define R128_CNTL_PAINT_MULTI 0x00009A00 337# define R128_CNTL_BITBLT_MULTI 0x00009B00 338# define R128_3D_RNDR_GEN_INDX_PRIM 0x00002300 339 340#define R128_CCE_PACKET_MASK 0xC0000000 341#define R128_CCE_PACKET_COUNT_MASK 0x3fff0000 342#define R128_CCE_PACKET0_REG_MASK 0x000007ff 343#define R128_CCE_PACKET1_REG0_MASK 0x000007ff 344#define R128_CCE_PACKET1_REG1_MASK 0x003ff800 345 346#define R128_CCE_VC_CNTL_PRIM_TYPE_NONE 0x00000000 347#define R128_CCE_VC_CNTL_PRIM_TYPE_POINT 0x00000001 348#define R128_CCE_VC_CNTL_PRIM_TYPE_LINE 0x00000002 349#define R128_CCE_VC_CNTL_PRIM_TYPE_POLY_LINE 0x00000003 350#define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_LIST 0x00000004 351#define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_FAN 0x00000005 352#define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_STRIP 0x00000006 353#define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_TYPE2 0x00000007 354#define R128_CCE_VC_CNTL_PRIM_WALK_IND 0x00000010 355#define R128_CCE_VC_CNTL_PRIM_WALK_LIST 0x00000020 356#define R128_CCE_VC_CNTL_PRIM_WALK_RING 0x00000030 357#define R128_CCE_VC_CNTL_NUM_SHIFT 16 358 359#define R128_DATATYPE_VQ 0 360#define R128_DATATYPE_CI4 1 361#define R128_DATATYPE_CI8 2 362#define R128_DATATYPE_ARGB1555 3 363#define R128_DATATYPE_RGB565 4 364#define R128_DATATYPE_RGB888 5 365#define R128_DATATYPE_ARGB8888 6 366#define R128_DATATYPE_RGB332 7 367#define R128_DATATYPE_Y8 8 368#define R128_DATATYPE_RGB8 9 369#define R128_DATATYPE_CI16 10 370#define R128_DATATYPE_YVYU422 11 371#define R128_DATATYPE_VYUY422 12 372#define R128_DATATYPE_AYUV444 14 373#define R128_DATATYPE_ARGB4444 15 374 375/* Constants */ 376#define R128_AGP_OFFSET 0x02000000 377 378#define R128_WATERMARK_L 16 379#define R128_WATERMARK_M 8 380#define R128_WATERMARK_N 8 381#define R128_WATERMARK_K 128 382 383#define R128_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 384 385#define R128_LAST_FRAME_REG R128_GUI_SCRATCH_REG0 386#define R128_LAST_DISPATCH_REG R128_GUI_SCRATCH_REG1 387#define R128_MAX_VB_AGE 0x7fffffff 388#define R128_MAX_VB_VERTS (0xffff) 389 390#define R128_RING_HIGH_MARK 128 391 392#define R128_PERFORMANCE_BOXES 0 393 394#define R128_PCIGART_TABLE_SIZE 32768 395 396#define R128_READ(reg) DRM_READ32( dev_priv->mmio, (reg) ) 397#define R128_WRITE(reg,val) DRM_WRITE32( dev_priv->mmio, (reg), (val) ) 398#define R128_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) ) 399#define R128_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) ) 400 401#define R128_WRITE_PLL(addr,val) \ 402do { \ 403 R128_WRITE8(R128_CLOCK_CNTL_INDEX, \ 404 ((addr) & 0x1f) | R128_PLL_WR_EN); \ 405 R128_WRITE(R128_CLOCK_CNTL_DATA, (val)); \ 406} while (0) 407 408#define CCE_PACKET0( reg, n ) (R128_CCE_PACKET0 | \ 409 ((n) << 16) | ((reg) >> 2)) 410#define CCE_PACKET1( reg0, reg1 ) (R128_CCE_PACKET1 | \ 411 (((reg1) >> 2) << 11) | ((reg0) >> 2)) 412#define CCE_PACKET2() (R128_CCE_PACKET2) 413#define CCE_PACKET3( pkt, n ) (R128_CCE_PACKET3 | \ 414 (pkt) | ((n) << 16)) 415 416static __inline__ void r128_update_ring_snapshot(drm_r128_private_t * dev_priv) 417{ 418 drm_r128_ring_buffer_t *ring = &dev_priv->ring; 419 ring->space = (GET_RING_HEAD(dev_priv) - ring->tail) * sizeof(u32); 420 if (ring->space <= 0) 421 ring->space += ring->size; 422} 423 424/* ================================================================ 425 * Misc helper macros 426 */ 427 428#define RING_SPACE_TEST_WITH_RETURN( dev_priv ) \ 429do { \ 430 drm_r128_ring_buffer_t *ring = &dev_priv->ring; int i; \ 431 if ( ring->space < ring->high_mark ) { \ 432 for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { \ 433 r128_update_ring_snapshot( dev_priv ); \ 434 if ( ring->space >= ring->high_mark ) \ 435 goto __ring_space_done; \ 436 DRM_UDELAY(1); \ 437 } \ 438 DRM_ERROR( "ring space check failed!\n" ); \ 439 return -EBUSY; \ 440 } \ 441 __ring_space_done: \ 442 ; \ 443} while (0) 444 445#define VB_AGE_TEST_WITH_RETURN( dev_priv ) \ 446do { \ 447 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; \ 448 if ( sarea_priv->last_dispatch >= R128_MAX_VB_AGE ) { \ 449 int __ret = r128_do_cce_idle( dev_priv ); \ 450 if ( __ret ) return __ret; \ 451 sarea_priv->last_dispatch = 0; \ 452 r128_freelist_reset( dev ); \ 453 } \ 454} while (0) 455 456#define R128_WAIT_UNTIL_PAGE_FLIPPED() do { \ 457 OUT_RING( CCE_PACKET0( R128_WAIT_UNTIL, 0 ) ); \ 458 OUT_RING( R128_EVENT_CRTC_OFFSET ); \ 459} while (0) 460 461/* ================================================================ 462 * Ring control 463 */ 464 465#define R128_VERBOSE 0 466 467#define RING_LOCALS \ 468 int write, _nr; unsigned int tail_mask; volatile u32 *ring; 469 470#define BEGIN_RING( n ) do { \ 471 if ( R128_VERBOSE ) { \ 472 DRM_INFO( "BEGIN_RING( %d )\n", (n)); \ 473 } \ 474 if ( dev_priv->ring.space <= (n) * sizeof(u32) ) { \ 475 COMMIT_RING(); \ 476 r128_wait_ring( dev_priv, (n) * sizeof(u32) ); \ 477 } \ 478 _nr = n; dev_priv->ring.space -= (n) * sizeof(u32); \ 479 ring = dev_priv->ring.start; \ 480 write = dev_priv->ring.tail; \ 481 tail_mask = dev_priv->ring.tail_mask; \ 482} while (0) 483 484/* You can set this to zero if you want. If the card locks up, you'll 485 * need to keep this set. It works around a bug in early revs of the 486 * Rage 128 chipset, where the CCE would read 32 dwords past the end of 487 * the ring buffer before wrapping around. 488 */ 489#define R128_BROKEN_CCE 1 490 491#define ADVANCE_RING() do { \ 492 if ( R128_VERBOSE ) { \ 493 DRM_INFO( "ADVANCE_RING() wr=0x%06x tail=0x%06x\n", \ 494 write, dev_priv->ring.tail ); \ 495 } \ 496 if ( R128_BROKEN_CCE && write < 32 ) { \ 497 memcpy( dev_priv->ring.end, \ 498 dev_priv->ring.start, \ 499 write * sizeof(u32) ); \ 500 } \ 501 if (((dev_priv->ring.tail + _nr) & tail_mask) != write) { \ 502 DRM_ERROR( \ 503 "ADVANCE_RING(): mismatch: nr: %x write: %x line: %d\n", \ 504 ((dev_priv->ring.tail + _nr) & tail_mask), \ 505 write, __LINE__); \ 506 } else \ 507 dev_priv->ring.tail = write; \ 508} while (0) 509 510#define COMMIT_RING() do { \ 511 if ( R128_VERBOSE ) { \ 512 DRM_INFO( "COMMIT_RING() tail=0x%06x\n", \ 513 dev_priv->ring.tail ); \ 514 } \ 515 DRM_MEMORYBARRIER(); \ 516 R128_WRITE( R128_PM4_BUFFER_DL_WPTR, dev_priv->ring.tail ); \ 517 R128_READ( R128_PM4_BUFFER_DL_WPTR ); \ 518} while (0) 519 520#define OUT_RING( x ) do { \ 521 if ( R128_VERBOSE ) { \ 522 DRM_INFO( " OUT_RING( 0x%08x ) at 0x%x\n", \ 523 (unsigned int)(x), write ); \ 524 } \ 525 ring[write++] = cpu_to_le32( x ); \ 526 write &= tail_mask; \ 527} while (0) 528 529#endif /* __R128_DRV_H__ */ 530