1/* savage_bci.c -- BCI support for Savage 2 * 3 * Copyright 2004 Felix Kuehling 4 * All Rights Reserved. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sub license, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the 14 * next paragraph) shall be included in all copies or substantial portions 15 * of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 20 * NON-INFRINGEMENT. IN NO EVENT SHALL FELIX KUEHLING BE LIABLE FOR 21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF 22 * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24 */ 25 26#include <sys/cdefs.h> 27__FBSDID("$FreeBSD$"); 28#include "dev/drm/drmP.h" 29#include "dev/drm/savage_drm.h" 30#include "dev/drm/savage_drv.h" 31 32/* Need a long timeout for shadow status updates can take a while 33 * and so can waiting for events when the queue is full. */ 34#define SAVAGE_DEFAULT_USEC_TIMEOUT 1000000 /* 1s */ 35#define SAVAGE_EVENT_USEC_TIMEOUT 5000000 /* 5s */ 36#define SAVAGE_FREELIST_DEBUG 0 37 38static int savage_do_cleanup_bci(struct drm_device *dev); 39 40static int 41savage_bci_wait_fifo_shadow(drm_savage_private_t *dev_priv, unsigned int n) 42{ 43 uint32_t mask = dev_priv->status_used_mask; 44 uint32_t threshold = dev_priv->bci_threshold_hi; 45 uint32_t status; 46 int i; 47 48#if SAVAGE_BCI_DEBUG 49 if (n > dev_priv->cob_size + SAVAGE_BCI_FIFO_SIZE - threshold) 50 DRM_ERROR("Trying to emit %d words " 51 "(more than guaranteed space in COB)\n", n); 52#endif 53 54 for (i = 0; i < SAVAGE_DEFAULT_USEC_TIMEOUT; i++) { 55 DRM_MEMORYBARRIER(); 56 status = dev_priv->status_ptr[0]; 57 if ((status & mask) < threshold) 58 return 0; 59 DRM_UDELAY(1); 60 } 61 62#if SAVAGE_BCI_DEBUG 63 DRM_ERROR("failed!\n"); 64 DRM_INFO(" status=0x%08x, threshold=0x%08x\n", status, threshold); 65#endif 66 return -EBUSY; 67} 68 69static int 70savage_bci_wait_fifo_s3d(drm_savage_private_t *dev_priv, unsigned int n) 71{ 72 uint32_t maxUsed = dev_priv->cob_size + SAVAGE_BCI_FIFO_SIZE - n; 73 uint32_t status; 74 int i; 75 76 for (i = 0; i < SAVAGE_DEFAULT_USEC_TIMEOUT; i++) { 77 status = SAVAGE_READ(SAVAGE_STATUS_WORD0); 78 if ((status & SAVAGE_FIFO_USED_MASK_S3D) <= maxUsed) 79 return 0; 80 DRM_UDELAY(1); 81 } 82 83#if SAVAGE_BCI_DEBUG 84 DRM_ERROR("failed!\n"); 85 DRM_INFO(" status=0x%08x\n", status); 86#endif 87 return -EBUSY; 88} 89 90static int 91savage_bci_wait_fifo_s4(drm_savage_private_t *dev_priv, unsigned int n) 92{ 93 uint32_t maxUsed = dev_priv->cob_size + SAVAGE_BCI_FIFO_SIZE - n; 94 uint32_t status; 95 int i; 96 97 for (i = 0; i < SAVAGE_DEFAULT_USEC_TIMEOUT; i++) { 98 status = SAVAGE_READ(SAVAGE_ALT_STATUS_WORD0); 99 if ((status & SAVAGE_FIFO_USED_MASK_S4) <= maxUsed) 100 return 0; 101 DRM_UDELAY(1); 102 } 103 104#if SAVAGE_BCI_DEBUG 105 DRM_ERROR("failed!\n"); 106 DRM_INFO(" status=0x%08x\n", status); 107#endif 108 return -EBUSY; 109} 110 111/* 112 * Waiting for events. 113 * 114 * The BIOSresets the event tag to 0 on mode changes. Therefore we 115 * never emit 0 to the event tag. If we find a 0 event tag we know the 116 * BIOS stomped on it and return success assuming that the BIOS waited 117 * for engine idle. 118 * 119 * Note: if the Xserver uses the event tag it has to follow the same 120 * rule. Otherwise there may be glitches every 2^16 events. 121 */ 122static int 123savage_bci_wait_event_shadow(drm_savage_private_t *dev_priv, uint16_t e) 124{ 125 uint32_t status; 126 int i; 127 128 for (i = 0; i < SAVAGE_EVENT_USEC_TIMEOUT; i++) { 129 DRM_MEMORYBARRIER(); 130 status = dev_priv->status_ptr[1]; 131 if ((((status & 0xffff) - e) & 0xffff) <= 0x7fff || 132 (status & 0xffff) == 0) 133 return 0; 134 DRM_UDELAY(1); 135 } 136 137#if SAVAGE_BCI_DEBUG 138 DRM_ERROR("failed!\n"); 139 DRM_INFO(" status=0x%08x, e=0x%04x\n", status, e); 140#endif 141 142 return -EBUSY; 143} 144 145static int 146savage_bci_wait_event_reg(drm_savage_private_t *dev_priv, uint16_t e) 147{ 148 uint32_t status; 149 int i; 150 151 for (i = 0; i < SAVAGE_EVENT_USEC_TIMEOUT; i++) { 152 status = SAVAGE_READ(SAVAGE_STATUS_WORD1); 153 if ((((status & 0xffff) - e) & 0xffff) <= 0x7fff || 154 (status & 0xffff) == 0) 155 return 0; 156 DRM_UDELAY(1); 157 } 158 159#if SAVAGE_BCI_DEBUG 160 DRM_ERROR("failed!\n"); 161 DRM_INFO(" status=0x%08x, e=0x%04x\n", status, e); 162#endif 163 164 return -EBUSY; 165} 166 167uint16_t savage_bci_emit_event(drm_savage_private_t *dev_priv, 168 unsigned int flags) 169{ 170 uint16_t count; 171 BCI_LOCALS; 172 173 if (dev_priv->status_ptr) { 174 /* coordinate with Xserver */ 175 count = dev_priv->status_ptr[1023]; 176 if (count < dev_priv->event_counter) 177 dev_priv->event_wrap++; 178 } else { 179 count = dev_priv->event_counter; 180 } 181 count = (count + 1) & 0xffff; 182 if (count == 0) { 183 count++; /* See the comment above savage_wait_event_*. */ 184 dev_priv->event_wrap++; 185 } 186 dev_priv->event_counter = count; 187 if (dev_priv->status_ptr) 188 dev_priv->status_ptr[1023] = (uint32_t)count; 189 190 if ((flags & (SAVAGE_WAIT_2D | SAVAGE_WAIT_3D))) { 191 unsigned int wait_cmd = BCI_CMD_WAIT; 192 if ((flags & SAVAGE_WAIT_2D)) 193 wait_cmd |= BCI_CMD_WAIT_2D; 194 if ((flags & SAVAGE_WAIT_3D)) 195 wait_cmd |= BCI_CMD_WAIT_3D; 196 BEGIN_BCI(2); 197 BCI_WRITE(wait_cmd); 198 } else { 199 BEGIN_BCI(1); 200 } 201 BCI_WRITE(BCI_CMD_UPDATE_EVENT_TAG | (uint32_t)count); 202 203 return count; 204} 205 206/* 207 * Freelist management 208 */ 209static int savage_freelist_init(struct drm_device *dev) 210{ 211 drm_savage_private_t *dev_priv = dev->dev_private; 212 struct drm_device_dma *dma = dev->dma; 213 struct drm_buf *buf; 214 drm_savage_buf_priv_t *entry; 215 int i; 216 DRM_DEBUG("count=%d\n", dma->buf_count); 217 218 dev_priv->head.next = &dev_priv->tail; 219 dev_priv->head.prev = NULL; 220 dev_priv->head.buf = NULL; 221 222 dev_priv->tail.next = NULL; 223 dev_priv->tail.prev = &dev_priv->head; 224 dev_priv->tail.buf = NULL; 225 226 for (i = 0; i < dma->buf_count; i++) { 227 buf = dma->buflist[i]; 228 entry = buf->dev_private; 229 230 SET_AGE(&entry->age, 0, 0); 231 entry->buf = buf; 232 233 entry->next = dev_priv->head.next; 234 entry->prev = &dev_priv->head; 235 dev_priv->head.next->prev = entry; 236 dev_priv->head.next = entry; 237 } 238 239 return 0; 240} 241 242static struct drm_buf *savage_freelist_get(struct drm_device *dev) 243{ 244 drm_savage_private_t *dev_priv = dev->dev_private; 245 drm_savage_buf_priv_t *tail = dev_priv->tail.prev; 246 uint16_t event; 247 unsigned int wrap; 248 DRM_DEBUG("\n"); 249 250 UPDATE_EVENT_COUNTER(); 251 if (dev_priv->status_ptr) 252 event = dev_priv->status_ptr[1] & 0xffff; 253 else 254 event = SAVAGE_READ(SAVAGE_STATUS_WORD1) & 0xffff; 255 wrap = dev_priv->event_wrap; 256 if (event > dev_priv->event_counter) 257 wrap--; /* hardware hasn't passed the last wrap yet */ 258 259 DRM_DEBUG(" tail=0x%04x %d\n", tail->age.event, tail->age.wrap); 260 DRM_DEBUG(" head=0x%04x %d\n", event, wrap); 261 262 if (tail->buf && (TEST_AGE(&tail->age, event, wrap) || event == 0)) { 263 drm_savage_buf_priv_t *next = tail->next; 264 drm_savage_buf_priv_t *prev = tail->prev; 265 prev->next = next; 266 next->prev = prev; 267 tail->next = tail->prev = NULL; 268 return tail->buf; 269 } 270 271 DRM_DEBUG("returning NULL, tail->buf=%p!\n", tail->buf); 272 return NULL; 273} 274 275void savage_freelist_put(struct drm_device *dev, struct drm_buf *buf) 276{ 277 drm_savage_private_t *dev_priv = dev->dev_private; 278 drm_savage_buf_priv_t *entry = buf->dev_private, *prev, *next; 279 280 DRM_DEBUG("age=0x%04x wrap=%d\n", entry->age.event, entry->age.wrap); 281 282 if (entry->next != NULL || entry->prev != NULL) { 283 DRM_ERROR("entry already on freelist.\n"); 284 return; 285 } 286 287 prev = &dev_priv->head; 288 next = prev->next; 289 prev->next = entry; 290 next->prev = entry; 291 entry->prev = prev; 292 entry->next = next; 293} 294 295/* 296 * Command DMA 297 */ 298static int savage_dma_init(drm_savage_private_t *dev_priv) 299{ 300 unsigned int i; 301 302 dev_priv->nr_dma_pages = dev_priv->cmd_dma->size / 303 (SAVAGE_DMA_PAGE_SIZE*4); 304 dev_priv->dma_pages = drm_alloc(sizeof(drm_savage_dma_page_t) * 305 dev_priv->nr_dma_pages, DRM_MEM_DRIVER); 306 if (dev_priv->dma_pages == NULL) 307 return -ENOMEM; 308 309 for (i = 0; i < dev_priv->nr_dma_pages; ++i) { 310 SET_AGE(&dev_priv->dma_pages[i].age, 0, 0); 311 dev_priv->dma_pages[i].used = 0; 312 dev_priv->dma_pages[i].flushed = 0; 313 } 314 SET_AGE(&dev_priv->last_dma_age, 0, 0); 315 316 dev_priv->first_dma_page = 0; 317 dev_priv->current_dma_page = 0; 318 319 return 0; 320} 321 322void savage_dma_reset(drm_savage_private_t *dev_priv) 323{ 324 uint16_t event; 325 unsigned int wrap, i; 326 event = savage_bci_emit_event(dev_priv, 0); 327 wrap = dev_priv->event_wrap; 328 for (i = 0; i < dev_priv->nr_dma_pages; ++i) { 329 SET_AGE(&dev_priv->dma_pages[i].age, event, wrap); 330 dev_priv->dma_pages[i].used = 0; 331 dev_priv->dma_pages[i].flushed = 0; 332 } 333 SET_AGE(&dev_priv->last_dma_age, event, wrap); 334 dev_priv->first_dma_page = dev_priv->current_dma_page = 0; 335} 336 337void savage_dma_wait(drm_savage_private_t *dev_priv, unsigned int page) 338{ 339 uint16_t event; 340 unsigned int wrap; 341 342 /* Faked DMA buffer pages don't age. */ 343 if (dev_priv->cmd_dma == &dev_priv->fake_dma) 344 return; 345 346 UPDATE_EVENT_COUNTER(); 347 if (dev_priv->status_ptr) 348 event = dev_priv->status_ptr[1] & 0xffff; 349 else 350 event = SAVAGE_READ(SAVAGE_STATUS_WORD1) & 0xffff; 351 wrap = dev_priv->event_wrap; 352 if (event > dev_priv->event_counter) 353 wrap--; /* hardware hasn't passed the last wrap yet */ 354 355 if (dev_priv->dma_pages[page].age.wrap > wrap || 356 (dev_priv->dma_pages[page].age.wrap == wrap && 357 dev_priv->dma_pages[page].age.event > event)) { 358 if (dev_priv->wait_evnt(dev_priv, 359 dev_priv->dma_pages[page].age.event) 360 < 0) 361 DRM_ERROR("wait_evnt failed!\n"); 362 } 363} 364 365uint32_t *savage_dma_alloc(drm_savage_private_t *dev_priv, unsigned int n) 366{ 367 unsigned int cur = dev_priv->current_dma_page; 368 unsigned int rest = SAVAGE_DMA_PAGE_SIZE - 369 dev_priv->dma_pages[cur].used; 370 unsigned int nr_pages = (n - rest + SAVAGE_DMA_PAGE_SIZE - 1) / 371 SAVAGE_DMA_PAGE_SIZE; 372 uint32_t *dma_ptr; 373 unsigned int i; 374 375 DRM_DEBUG("cur=%u, cur->used=%u, n=%u, rest=%u, nr_pages=%u\n", 376 cur, dev_priv->dma_pages[cur].used, n, rest, nr_pages); 377 378 if (cur + nr_pages < dev_priv->nr_dma_pages) { 379 dma_ptr = (uint32_t *)dev_priv->cmd_dma->virtual + 380 cur * SAVAGE_DMA_PAGE_SIZE + dev_priv->dma_pages[cur].used; 381 if (n < rest) 382 rest = n; 383 dev_priv->dma_pages[cur].used += rest; 384 n -= rest; 385 cur++; 386 } else { 387 dev_priv->dma_flush(dev_priv); 388 nr_pages = 389 (n + SAVAGE_DMA_PAGE_SIZE - 1) / SAVAGE_DMA_PAGE_SIZE; 390 for (i = cur; i < dev_priv->nr_dma_pages; ++i) { 391 dev_priv->dma_pages[i].age = dev_priv->last_dma_age; 392 dev_priv->dma_pages[i].used = 0; 393 dev_priv->dma_pages[i].flushed = 0; 394 } 395 dma_ptr = (uint32_t *)dev_priv->cmd_dma->virtual; 396 dev_priv->first_dma_page = cur = 0; 397 } 398 for (i = cur; nr_pages > 0; ++i, --nr_pages) { 399#if SAVAGE_DMA_DEBUG 400 if (dev_priv->dma_pages[i].used) { 401 DRM_ERROR("unflushed page %u: used=%u\n", 402 i, dev_priv->dma_pages[i].used); 403 } 404#endif 405 if (n > SAVAGE_DMA_PAGE_SIZE) 406 dev_priv->dma_pages[i].used = SAVAGE_DMA_PAGE_SIZE; 407 else 408 dev_priv->dma_pages[i].used = n; 409 n -= SAVAGE_DMA_PAGE_SIZE; 410 } 411 dev_priv->current_dma_page = --i; 412 413 DRM_DEBUG("cur=%u, cur->used=%u, n=%u\n", 414 i, dev_priv->dma_pages[i].used, n); 415 416 savage_dma_wait(dev_priv, dev_priv->current_dma_page); 417 418 return dma_ptr; 419} 420 421static void savage_dma_flush(drm_savage_private_t *dev_priv) 422{ 423 unsigned int first = dev_priv->first_dma_page; 424 unsigned int cur = dev_priv->current_dma_page; 425 uint16_t event; 426 unsigned int wrap, pad, align, len, i; 427 unsigned long phys_addr; 428 BCI_LOCALS; 429 430 if (first == cur && 431 dev_priv->dma_pages[cur].used == dev_priv->dma_pages[cur].flushed) 432 return; 433 434 /* pad length to multiples of 2 entries 435 * align start of next DMA block to multiles of 8 entries */ 436 pad = -dev_priv->dma_pages[cur].used & 1; 437 align = -(dev_priv->dma_pages[cur].used + pad) & 7; 438 439 DRM_DEBUG("first=%u, cur=%u, first->flushed=%u, cur->used=%u, " 440 "pad=%u, align=%u\n", 441 first, cur, dev_priv->dma_pages[first].flushed, 442 dev_priv->dma_pages[cur].used, pad, align); 443 444 /* pad with noops */ 445 if (pad) { 446 uint32_t *dma_ptr = (uint32_t *)dev_priv->cmd_dma->virtual + 447 cur * SAVAGE_DMA_PAGE_SIZE + dev_priv->dma_pages[cur].used; 448 dev_priv->dma_pages[cur].used += pad; 449 while (pad != 0) { 450 *dma_ptr++ = BCI_CMD_WAIT; 451 pad--; 452 } 453 } 454 455 DRM_MEMORYBARRIER(); 456 457 /* do flush ... */ 458 phys_addr = dev_priv->cmd_dma->offset + 459 (first * SAVAGE_DMA_PAGE_SIZE + 460 dev_priv->dma_pages[first].flushed) * 4; 461 len = (cur - first) * SAVAGE_DMA_PAGE_SIZE + 462 dev_priv->dma_pages[cur].used - dev_priv->dma_pages[first].flushed; 463 464 DRM_DEBUG("phys_addr=%lx, len=%u\n", 465 phys_addr | dev_priv->dma_type, len); 466 467 BEGIN_BCI(3); 468 BCI_SET_REGISTERS(SAVAGE_DMABUFADDR, 1); 469 BCI_WRITE(phys_addr | dev_priv->dma_type); 470 BCI_DMA(len); 471 472 /* fix alignment of the start of the next block */ 473 dev_priv->dma_pages[cur].used += align; 474 475 /* age DMA pages */ 476 event = savage_bci_emit_event(dev_priv, 0); 477 wrap = dev_priv->event_wrap; 478 for (i = first; i < cur; ++i) { 479 SET_AGE(&dev_priv->dma_pages[i].age, event, wrap); 480 dev_priv->dma_pages[i].used = 0; 481 dev_priv->dma_pages[i].flushed = 0; 482 } 483 /* age the current page only when it's full */ 484 if (dev_priv->dma_pages[cur].used == SAVAGE_DMA_PAGE_SIZE) { 485 SET_AGE(&dev_priv->dma_pages[cur].age, event, wrap); 486 dev_priv->dma_pages[cur].used = 0; 487 dev_priv->dma_pages[cur].flushed = 0; 488 /* advance to next page */ 489 cur++; 490 if (cur == dev_priv->nr_dma_pages) 491 cur = 0; 492 dev_priv->first_dma_page = dev_priv->current_dma_page = cur; 493 } else { 494 dev_priv->first_dma_page = cur; 495 dev_priv->dma_pages[cur].flushed = dev_priv->dma_pages[i].used; 496 } 497 SET_AGE(&dev_priv->last_dma_age, event, wrap); 498 499 DRM_DEBUG("first=cur=%u, cur->used=%u, cur->flushed=%u\n", cur, 500 dev_priv->dma_pages[cur].used, 501 dev_priv->dma_pages[cur].flushed); 502} 503 504static void savage_fake_dma_flush(drm_savage_private_t *dev_priv) 505{ 506 unsigned int i, j; 507 BCI_LOCALS; 508 509 if (dev_priv->first_dma_page == dev_priv->current_dma_page && 510 dev_priv->dma_pages[dev_priv->current_dma_page].used == 0) 511 return; 512 513 DRM_DEBUG("first=%u, cur=%u, cur->used=%u\n", 514 dev_priv->first_dma_page, dev_priv->current_dma_page, 515 dev_priv->dma_pages[dev_priv->current_dma_page].used); 516 517 for (i = dev_priv->first_dma_page; 518 i <= dev_priv->current_dma_page && dev_priv->dma_pages[i].used; 519 ++i) { 520 uint32_t *dma_ptr = (uint32_t *)dev_priv->cmd_dma->virtual + 521 i * SAVAGE_DMA_PAGE_SIZE; 522#if SAVAGE_DMA_DEBUG 523 /* Sanity check: all pages except the last one must be full. */ 524 if (i < dev_priv->current_dma_page && 525 dev_priv->dma_pages[i].used != SAVAGE_DMA_PAGE_SIZE) { 526 DRM_ERROR("partial DMA page %u: used=%u", 527 i, dev_priv->dma_pages[i].used); 528 } 529#endif 530 BEGIN_BCI(dev_priv->dma_pages[i].used); 531 for (j = 0; j < dev_priv->dma_pages[i].used; ++j) { 532 BCI_WRITE(dma_ptr[j]); 533 } 534 dev_priv->dma_pages[i].used = 0; 535 } 536 537 /* reset to first page */ 538 dev_priv->first_dma_page = dev_priv->current_dma_page = 0; 539} 540 541int savage_driver_load(struct drm_device *dev, unsigned long chipset) 542{ 543 drm_savage_private_t *dev_priv; 544 545 dev_priv = drm_alloc(sizeof(drm_savage_private_t), DRM_MEM_DRIVER); 546 if (dev_priv == NULL) 547 return -ENOMEM; 548 549 memset(dev_priv, 0, sizeof(drm_savage_private_t)); 550 dev->dev_private = (void *)dev_priv; 551 552 dev_priv->chipset = (enum savage_family)chipset; 553 554 return 0; 555} 556 557/* 558 * Initialize mappings. On Savage4 and SavageIX the alignment 559 * and size of the aperture is not suitable for automatic MTRR setup 560 * in drm_addmap. Therefore we add them manually before the maps are 561 * initialized, and tear them down on last close. 562 */ 563int savage_driver_firstopen(struct drm_device *dev) 564{ 565 drm_savage_private_t *dev_priv = dev->dev_private; 566 unsigned long mmio_base, fb_base, fb_size, aperture_base; 567 /* fb_rsrc and aper_rsrc aren't really used currently, but still exist 568 * in case we decide we need information on the BAR for BSD in the 569 * future. 570 */ 571 unsigned int fb_rsrc, aper_rsrc; 572 int ret = 0; 573 574 dev_priv->mtrr[0].handle = -1; 575 dev_priv->mtrr[1].handle = -1; 576 dev_priv->mtrr[2].handle = -1; 577 if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) { 578 fb_rsrc = 0; 579 fb_base = drm_get_resource_start(dev, 0); 580 fb_size = SAVAGE_FB_SIZE_S3; 581 mmio_base = fb_base + SAVAGE_FB_SIZE_S3; 582 aper_rsrc = 0; 583 aperture_base = fb_base + SAVAGE_APERTURE_OFFSET; 584 /* this should always be true */ 585 if (drm_get_resource_len(dev, 0) == 0x08000000) { 586 /* Don't make MMIO write-cobining! We need 3 587 * MTRRs. */ 588 dev_priv->mtrr[0].base = fb_base; 589 dev_priv->mtrr[0].size = 0x01000000; 590 dev_priv->mtrr[0].handle = 591 drm_mtrr_add(dev_priv->mtrr[0].base, 592 dev_priv->mtrr[0].size, DRM_MTRR_WC); 593 dev_priv->mtrr[1].base = fb_base + 0x02000000; 594 dev_priv->mtrr[1].size = 0x02000000; 595 dev_priv->mtrr[1].handle = 596 drm_mtrr_add(dev_priv->mtrr[1].base, 597 dev_priv->mtrr[1].size, DRM_MTRR_WC); 598 dev_priv->mtrr[2].base = fb_base + 0x04000000; 599 dev_priv->mtrr[2].size = 0x04000000; 600 dev_priv->mtrr[2].handle = 601 drm_mtrr_add(dev_priv->mtrr[2].base, 602 dev_priv->mtrr[2].size, DRM_MTRR_WC); 603 } else { 604 DRM_ERROR("strange pci_resource_len %08lx\n", 605 drm_get_resource_len(dev, 0)); 606 } 607 } else if (dev_priv->chipset != S3_SUPERSAVAGE && 608 dev_priv->chipset != S3_SAVAGE2000) { 609 mmio_base = drm_get_resource_start(dev, 0); 610 fb_rsrc = 1; 611 fb_base = drm_get_resource_start(dev, 1); 612 fb_size = SAVAGE_FB_SIZE_S4; 613 aper_rsrc = 1; 614 aperture_base = fb_base + SAVAGE_APERTURE_OFFSET; 615 /* this should always be true */ 616 if (drm_get_resource_len(dev, 1) == 0x08000000) { 617 /* Can use one MTRR to cover both fb and 618 * aperture. */ 619 dev_priv->mtrr[0].base = fb_base; 620 dev_priv->mtrr[0].size = 0x08000000; 621 dev_priv->mtrr[0].handle = 622 drm_mtrr_add(dev_priv->mtrr[0].base, 623 dev_priv->mtrr[0].size, DRM_MTRR_WC); 624 } else { 625 DRM_ERROR("strange pci_resource_len %08lx\n", 626 drm_get_resource_len(dev, 1)); 627 } 628 } else { 629 mmio_base = drm_get_resource_start(dev, 0); 630 fb_rsrc = 1; 631 fb_base = drm_get_resource_start(dev, 1); 632 fb_size = drm_get_resource_len(dev, 1); 633 aper_rsrc = 2; 634 aperture_base = drm_get_resource_start(dev, 2); 635 /* Automatic MTRR setup will do the right thing. */ 636 } 637 638 ret = drm_addmap(dev, mmio_base, SAVAGE_MMIO_SIZE, _DRM_REGISTERS, 639 _DRM_READ_ONLY, &dev_priv->mmio); 640 if (ret) 641 return ret; 642 643 ret = drm_addmap(dev, fb_base, fb_size, _DRM_FRAME_BUFFER, 644 _DRM_WRITE_COMBINING, &dev_priv->fb); 645 if (ret) 646 return ret; 647 648 ret = drm_addmap(dev, aperture_base, SAVAGE_APERTURE_SIZE, 649 _DRM_FRAME_BUFFER, _DRM_WRITE_COMBINING, 650 &dev_priv->aperture); 651 if (ret) 652 return ret; 653 654 return ret; 655} 656 657/* 658 * Delete MTRRs and free device-private data. 659 */ 660void savage_driver_lastclose(struct drm_device *dev) 661{ 662 drm_savage_private_t *dev_priv = dev->dev_private; 663 int i; 664 665 for (i = 0; i < 3; ++i) 666 if (dev_priv->mtrr[i].handle >= 0) 667 drm_mtrr_del(dev_priv->mtrr[i].handle, 668 dev_priv->mtrr[i].base, 669 dev_priv->mtrr[i].size, DRM_MTRR_WC); 670} 671 672int savage_driver_unload(struct drm_device *dev) 673{ 674 drm_savage_private_t *dev_priv = dev->dev_private; 675 676 drm_free(dev_priv, sizeof(drm_savage_private_t), DRM_MEM_DRIVER); 677 678 return 0; 679} 680 681static int savage_do_init_bci(struct drm_device *dev, drm_savage_init_t *init) 682{ 683 drm_savage_private_t *dev_priv = dev->dev_private; 684 685 if (init->fb_bpp != 16 && init->fb_bpp != 32) { 686 DRM_ERROR("invalid frame buffer bpp %d!\n", init->fb_bpp); 687 return -EINVAL; 688 } 689 if (init->depth_bpp != 16 && init->depth_bpp != 32) { 690 DRM_ERROR("invalid depth buffer bpp %d!\n", init->fb_bpp); 691 return -EINVAL; 692 } 693 if (init->dma_type != SAVAGE_DMA_AGP && 694 init->dma_type != SAVAGE_DMA_PCI) { 695 DRM_ERROR("invalid dma memory type %d!\n", init->dma_type); 696 return -EINVAL; 697 } 698 699 dev_priv->cob_size = init->cob_size; 700 dev_priv->bci_threshold_lo = init->bci_threshold_lo; 701 dev_priv->bci_threshold_hi = init->bci_threshold_hi; 702 dev_priv->dma_type = init->dma_type; 703 704 dev_priv->fb_bpp = init->fb_bpp; 705 dev_priv->front_offset = init->front_offset; 706 dev_priv->front_pitch = init->front_pitch; 707 dev_priv->back_offset = init->back_offset; 708 dev_priv->back_pitch = init->back_pitch; 709 dev_priv->depth_bpp = init->depth_bpp; 710 dev_priv->depth_offset = init->depth_offset; 711 dev_priv->depth_pitch = init->depth_pitch; 712 713 dev_priv->texture_offset = init->texture_offset; 714 dev_priv->texture_size = init->texture_size; 715 716 dev_priv->sarea = drm_getsarea(dev); 717 if (!dev_priv->sarea) { 718 DRM_ERROR("could not find sarea!\n"); 719 savage_do_cleanup_bci(dev); 720 return -EINVAL; 721 } 722 if (init->status_offset != 0) { 723 dev_priv->status = drm_core_findmap(dev, init->status_offset); 724 if (!dev_priv->status) { 725 DRM_ERROR("could not find shadow status region!\n"); 726 savage_do_cleanup_bci(dev); 727 return -EINVAL; 728 } 729 } else { 730 dev_priv->status = NULL; 731 } 732 if (dev_priv->dma_type == SAVAGE_DMA_AGP && init->buffers_offset) { 733 dev->agp_buffer_token = init->buffers_offset; 734 dev->agp_buffer_map = drm_core_findmap(dev, 735 init->buffers_offset); 736 if (!dev->agp_buffer_map) { 737 DRM_ERROR("could not find DMA buffer region!\n"); 738 savage_do_cleanup_bci(dev); 739 return -EINVAL; 740 } 741 drm_core_ioremap(dev->agp_buffer_map, dev); 742 if (!dev->agp_buffer_map) { 743 DRM_ERROR("failed to ioremap DMA buffer region!\n"); 744 savage_do_cleanup_bci(dev); 745 return -ENOMEM; 746 } 747 } 748 if (init->agp_textures_offset) { 749 dev_priv->agp_textures = 750 drm_core_findmap(dev, init->agp_textures_offset); 751 if (!dev_priv->agp_textures) { 752 DRM_ERROR("could not find agp texture region!\n"); 753 savage_do_cleanup_bci(dev); 754 return -EINVAL; 755 } 756 } else { 757 dev_priv->agp_textures = NULL; 758 } 759 760 if (init->cmd_dma_offset) { 761 if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) { 762 DRM_ERROR("command DMA not supported on " 763 "Savage3D/MX/IX.\n"); 764 savage_do_cleanup_bci(dev); 765 return -EINVAL; 766 } 767 if (dev->dma && dev->dma->buflist) { 768 DRM_ERROR("command and vertex DMA not supported " 769 "at the same time.\n"); 770 savage_do_cleanup_bci(dev); 771 return -EINVAL; 772 } 773 dev_priv->cmd_dma = drm_core_findmap(dev, init->cmd_dma_offset); 774 if (!dev_priv->cmd_dma) { 775 DRM_ERROR("could not find command DMA region!\n"); 776 savage_do_cleanup_bci(dev); 777 return -EINVAL; 778 } 779 if (dev_priv->dma_type == SAVAGE_DMA_AGP) { 780 if (dev_priv->cmd_dma->type != _DRM_AGP) { 781 DRM_ERROR("AGP command DMA region is not a " 782 "_DRM_AGP map!\n"); 783 savage_do_cleanup_bci(dev); 784 return -EINVAL; 785 } 786 drm_core_ioremap(dev_priv->cmd_dma, dev); 787 if (!dev_priv->cmd_dma->virtual) { 788 DRM_ERROR("failed to ioremap command " 789 "DMA region!\n"); 790 savage_do_cleanup_bci(dev); 791 return -ENOMEM; 792 } 793 } else if (dev_priv->cmd_dma->type != _DRM_CONSISTENT) { 794 DRM_ERROR("PCI command DMA region is not a " 795 "_DRM_CONSISTENT map!\n"); 796 savage_do_cleanup_bci(dev); 797 return -EINVAL; 798 } 799 } else { 800 dev_priv->cmd_dma = NULL; 801 } 802 803 dev_priv->dma_flush = savage_dma_flush; 804 if (!dev_priv->cmd_dma) { 805 DRM_DEBUG("falling back to faked command DMA.\n"); 806 dev_priv->fake_dma.offset = 0; 807 dev_priv->fake_dma.size = SAVAGE_FAKE_DMA_SIZE; 808 dev_priv->fake_dma.type = _DRM_SHM; 809 dev_priv->fake_dma.virtual = drm_alloc(SAVAGE_FAKE_DMA_SIZE, 810 DRM_MEM_DRIVER); 811 if (!dev_priv->fake_dma.virtual) { 812 DRM_ERROR("could not allocate faked DMA buffer!\n"); 813 savage_do_cleanup_bci(dev); 814 return -ENOMEM; 815 } 816 dev_priv->cmd_dma = &dev_priv->fake_dma; 817 dev_priv->dma_flush = savage_fake_dma_flush; 818 } 819 820 dev_priv->sarea_priv = 821 (drm_savage_sarea_t *)((uint8_t *)dev_priv->sarea->virtual + 822 init->sarea_priv_offset); 823 824 /* setup bitmap descriptors */ 825 { 826 unsigned int color_tile_format; 827 unsigned int depth_tile_format; 828 unsigned int front_stride, back_stride, depth_stride; 829 if (dev_priv->chipset <= S3_SAVAGE4) { 830 color_tile_format = dev_priv->fb_bpp == 16 ? 831 SAVAGE_BD_TILE_16BPP : SAVAGE_BD_TILE_32BPP; 832 depth_tile_format = dev_priv->depth_bpp == 16 ? 833 SAVAGE_BD_TILE_16BPP : SAVAGE_BD_TILE_32BPP; 834 } else { 835 color_tile_format = SAVAGE_BD_TILE_DEST; 836 depth_tile_format = SAVAGE_BD_TILE_DEST; 837 } 838 front_stride = dev_priv->front_pitch / (dev_priv->fb_bpp / 8); 839 back_stride = dev_priv->back_pitch / (dev_priv->fb_bpp / 8); 840 depth_stride = 841 dev_priv->depth_pitch / (dev_priv->depth_bpp / 8); 842 843 dev_priv->front_bd = front_stride | SAVAGE_BD_BW_DISABLE | 844 (dev_priv->fb_bpp << SAVAGE_BD_BPP_SHIFT) | 845 (color_tile_format << SAVAGE_BD_TILE_SHIFT); 846 847 dev_priv-> back_bd = back_stride | SAVAGE_BD_BW_DISABLE | 848 (dev_priv->fb_bpp << SAVAGE_BD_BPP_SHIFT) | 849 (color_tile_format << SAVAGE_BD_TILE_SHIFT); 850 851 dev_priv->depth_bd = depth_stride | SAVAGE_BD_BW_DISABLE | 852 (dev_priv->depth_bpp << SAVAGE_BD_BPP_SHIFT) | 853 (depth_tile_format << SAVAGE_BD_TILE_SHIFT); 854 } 855 856 /* setup status and bci ptr */ 857 dev_priv->event_counter = 0; 858 dev_priv->event_wrap = 0; 859 dev_priv->bci_ptr = (volatile uint32_t *) 860 ((uint8_t *)dev_priv->mmio->virtual + SAVAGE_BCI_OFFSET); 861 if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) { 862 dev_priv->status_used_mask = SAVAGE_FIFO_USED_MASK_S3D; 863 } else { 864 dev_priv->status_used_mask = SAVAGE_FIFO_USED_MASK_S4; 865 } 866 if (dev_priv->status != NULL) { 867 dev_priv->status_ptr = 868 (volatile uint32_t *)dev_priv->status->virtual; 869 dev_priv->wait_fifo = savage_bci_wait_fifo_shadow; 870 dev_priv->wait_evnt = savage_bci_wait_event_shadow; 871 dev_priv->status_ptr[1023] = dev_priv->event_counter; 872 } else { 873 dev_priv->status_ptr = NULL; 874 if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) { 875 dev_priv->wait_fifo = savage_bci_wait_fifo_s3d; 876 } else { 877 dev_priv->wait_fifo = savage_bci_wait_fifo_s4; 878 } 879 dev_priv->wait_evnt = savage_bci_wait_event_reg; 880 } 881 882 /* cliprect functions */ 883 if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) 884 dev_priv->emit_clip_rect = savage_emit_clip_rect_s3d; 885 else 886 dev_priv->emit_clip_rect = savage_emit_clip_rect_s4; 887 888 if (savage_freelist_init(dev) < 0) { 889 DRM_ERROR("could not initialize freelist\n"); 890 savage_do_cleanup_bci(dev); 891 return -ENOMEM; 892 } 893 894 if (savage_dma_init(dev_priv) < 0) { 895 DRM_ERROR("could not initialize command DMA\n"); 896 savage_do_cleanup_bci(dev); 897 return -ENOMEM; 898 } 899 900 return 0; 901} 902 903static int savage_do_cleanup_bci(struct drm_device *dev) 904{ 905 drm_savage_private_t *dev_priv = dev->dev_private; 906 907 if (dev_priv->cmd_dma == &dev_priv->fake_dma) { 908 if (dev_priv->fake_dma.virtual) 909 drm_free(dev_priv->fake_dma.virtual, 910 SAVAGE_FAKE_DMA_SIZE, DRM_MEM_DRIVER); 911 } else if (dev_priv->cmd_dma && dev_priv->cmd_dma->virtual && 912 dev_priv->cmd_dma->type == _DRM_AGP && 913 dev_priv->dma_type == SAVAGE_DMA_AGP) 914 drm_core_ioremapfree(dev_priv->cmd_dma, dev); 915 916 if (dev_priv->dma_type == SAVAGE_DMA_AGP && 917 dev->agp_buffer_map && dev->agp_buffer_map->virtual) { 918 drm_core_ioremapfree(dev->agp_buffer_map, dev); 919 /* make sure the next instance (which may be running 920 * in PCI mode) doesn't try to use an old 921 * agp_buffer_map. */ 922 dev->agp_buffer_map = NULL; 923 } 924 925 if (dev_priv->dma_pages) 926 drm_free(dev_priv->dma_pages, 927 sizeof(drm_savage_dma_page_t)*dev_priv->nr_dma_pages, 928 DRM_MEM_DRIVER); 929 930 return 0; 931} 932 933static int savage_bci_init(struct drm_device *dev, void *data, struct drm_file *file_priv) 934{ 935 drm_savage_init_t *init = data; 936 937 LOCK_TEST_WITH_RETURN(dev, file_priv); 938 939 switch (init->func) { 940 case SAVAGE_INIT_BCI: 941 return savage_do_init_bci(dev, init); 942 case SAVAGE_CLEANUP_BCI: 943 return savage_do_cleanup_bci(dev); 944 } 945 946 return -EINVAL; 947} 948 949static int savage_bci_event_emit(struct drm_device *dev, void *data, struct drm_file *file_priv) 950{ 951 drm_savage_private_t *dev_priv = dev->dev_private; 952 drm_savage_event_emit_t *event = data; 953 954 DRM_DEBUG("\n"); 955 956 LOCK_TEST_WITH_RETURN(dev, file_priv); 957 958 event->count = savage_bci_emit_event(dev_priv, event->flags); 959 event->count |= dev_priv->event_wrap << 16; 960 961 return 0; 962} 963 964static int savage_bci_event_wait(struct drm_device *dev, void *data, struct drm_file *file_priv) 965{ 966 drm_savage_private_t *dev_priv = dev->dev_private; 967 drm_savage_event_wait_t *event = data; 968 unsigned int event_e, hw_e; 969 unsigned int event_w, hw_w; 970 971 DRM_DEBUG("\n"); 972 973 UPDATE_EVENT_COUNTER(); 974 if (dev_priv->status_ptr) 975 hw_e = dev_priv->status_ptr[1] & 0xffff; 976 else 977 hw_e = SAVAGE_READ(SAVAGE_STATUS_WORD1) & 0xffff; 978 hw_w = dev_priv->event_wrap; 979 if (hw_e > dev_priv->event_counter) 980 hw_w--; /* hardware hasn't passed the last wrap yet */ 981 982 event_e = event->count & 0xffff; 983 event_w = event->count >> 16; 984 985 /* Don't need to wait if 986 * - event counter wrapped since the event was emitted or 987 * - the hardware has advanced up to or over the event to wait for. 988 */ 989 if (event_w < hw_w || (event_w == hw_w && event_e <= hw_e)) 990 return 0; 991 else 992 return dev_priv->wait_evnt(dev_priv, event_e); 993} 994 995/* 996 * DMA buffer management 997 */ 998 999static int savage_bci_get_buffers(struct drm_device *dev, 1000 struct drm_file *file_priv, 1001 struct drm_dma *d) 1002{ 1003 struct drm_buf *buf; 1004 int i; 1005 1006 for (i = d->granted_count; i < d->request_count; i++) { 1007 buf = savage_freelist_get(dev); 1008 if (!buf) 1009 return -EAGAIN; 1010 1011 buf->file_priv = file_priv; 1012 1013 if (DRM_COPY_TO_USER(&d->request_indices[i], 1014 &buf->idx, sizeof(buf->idx))) 1015 return -EFAULT; 1016 if (DRM_COPY_TO_USER(&d->request_sizes[i], 1017 &buf->total, sizeof(buf->total))) 1018 return -EFAULT; 1019 1020 d->granted_count++; 1021 } 1022 return 0; 1023} 1024 1025int savage_bci_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv) 1026{ 1027 struct drm_device_dma *dma = dev->dma; 1028 struct drm_dma *d = data; 1029 int ret = 0; 1030 1031 LOCK_TEST_WITH_RETURN(dev, file_priv); 1032 1033 /* Please don't send us buffers. 1034 */ 1035 if (d->send_count != 0) { 1036 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n", 1037 DRM_CURRENTPID, d->send_count); 1038 return -EINVAL; 1039 } 1040 1041 /* We'll send you buffers. 1042 */ 1043 if (d->request_count < 0 || d->request_count > dma->buf_count) { 1044 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n", 1045 DRM_CURRENTPID, d->request_count, dma->buf_count); 1046 return -EINVAL; 1047 } 1048 1049 d->granted_count = 0; 1050 1051 if (d->request_count) { 1052 ret = savage_bci_get_buffers(dev, file_priv, d); 1053 } 1054 1055 return ret; 1056} 1057 1058void savage_reclaim_buffers(struct drm_device *dev, struct drm_file *file_priv) 1059{ 1060 struct drm_device_dma *dma = dev->dma; 1061 drm_savage_private_t *dev_priv = dev->dev_private; 1062 int i; 1063 1064 if (!dma) 1065 return; 1066 if (!dev_priv) 1067 return; 1068 if (!dma->buflist) 1069 return; 1070 1071 for (i = 0; i < dma->buf_count; i++) { 1072 struct drm_buf *buf = dma->buflist[i]; 1073 drm_savage_buf_priv_t *buf_priv = buf->dev_private; 1074 1075 if (buf->file_priv == file_priv && buf_priv && 1076 buf_priv->next == NULL && buf_priv->prev == NULL) { 1077 uint16_t event; 1078 DRM_DEBUG("reclaimed from client\n"); 1079 event = savage_bci_emit_event(dev_priv, SAVAGE_WAIT_3D); 1080 SET_AGE(&buf_priv->age, event, dev_priv->event_wrap); 1081 savage_freelist_put(dev, buf); 1082 } 1083 } 1084 1085 drm_core_reclaim_buffers(dev, file_priv); 1086} 1087 1088struct drm_ioctl_desc savage_ioctls[] = { 1089 DRM_IOCTL_DEF(DRM_SAVAGE_BCI_INIT, savage_bci_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1090 DRM_IOCTL_DEF(DRM_SAVAGE_BCI_CMDBUF, savage_bci_cmdbuf, DRM_AUTH), 1091 DRM_IOCTL_DEF(DRM_SAVAGE_BCI_EVENT_EMIT, savage_bci_event_emit, DRM_AUTH), 1092 DRM_IOCTL_DEF(DRM_SAVAGE_BCI_EVENT_WAIT, savage_bci_event_wait, DRM_AUTH), 1093}; 1094 1095int savage_max_ioctl = DRM_ARRAY_SIZE(savage_ioctls); 1096