Searched refs:control_reg (Results 1 - 15 of 15) sorted by relevance

/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/sound/pci/echoaudio/
H A Dechoaudio_3g.c141 static u32 set_spdif_bits(struct echoaudio *chip, u32 control_reg, u32 rate) argument
143 control_reg &= E3G_SPDIF_FORMAT_CLEAR_MASK;
147 control_reg |= E3G_SPDIF_SAMPLE_RATE0 | E3G_SPDIF_SAMPLE_RATE1;
151 control_reg |= E3G_SPDIF_SAMPLE_RATE0;
154 control_reg |= E3G_SPDIF_SAMPLE_RATE1;
159 control_reg |= E3G_SPDIF_PRO_MODE;
162 control_reg |= E3G_SPDIF_NOT_AUDIO;
164 control_reg |= E3G_SPDIF_24_BIT | E3G_SPDIF_TWO_CHANNEL |
167 return control_reg;
175 u32 control_reg; local
257 u32 control_reg, clock, base_rate, frq_reg; local
326 u32 control_reg, clocks_from_dsp; local
378 u32 control_reg; local
[all...]
H A Dgina24_dsp.c124 u32 control_reg; local
153 control_reg = GML_CONVERTER_ENABLE | GML_48KHZ;
154 err = write_control_reg(chip, control_reg, TRUE);
164 u32 control_reg, clock; local
181 control_reg = le32_to_cpu(chip->comm_page->control_register);
182 control_reg &= GML_CLOCK_CLEAR_MASK & GML_SPDIF_RATE_CLEAR_MASK;
197 if (control_reg & GML_SPDIF_PRO_MODE)
221 control_reg |= clock;
227 return write_control_reg(chip, control_reg, FALSE);
234 u32 control_reg, clocks_from_ds local
287 u32 control_reg; local
[all...]
H A Dlayla24_dsp.c159 u32 control_reg, clock, base_rate; local
175 control_reg = le32_to_cpu(chip->comm_page->control_register);
176 control_reg &= GML_CLOCK_CLEAR_MASK & GML_SPDIF_RATE_CLEAR_MASK;
193 if (control_reg & GML_SPDIF_PRO_MODE)
218 control_reg |= GML_DOUBLE_SPEED_MODE;
236 control_reg |= clock;
240 DE_ACT(("set_sample_rate: %d clock %d\n", rate, control_reg));
242 return write_control_reg(chip, control_reg, FALSE);
249 u32 control_reg, clocks_from_dsp; local
252 control_reg
333 u32 control_reg; local
[all...]
H A Dechoaudio_gml.c153 u32 control_reg; local
157 control_reg = le32_to_cpu(chip->comm_page->control_register);
158 control_reg &= GML_SPDIF_FORMAT_CLEAR_MASK;
161 control_reg |= GML_SPDIF_TWO_CHANNEL | GML_SPDIF_24_BIT |
165 control_reg |= GML_SPDIF_PRO_MODE;
169 control_reg |= GML_SPDIF_SAMPLE_RATE0 |
173 control_reg |= GML_SPDIF_SAMPLE_RATE0;
176 control_reg |= GML_SPDIF_SAMPLE_RATE1;
183 control_reg |= GML_SPDIF_SAMPLE_RATE0 |
187 control_reg |
[all...]
H A Dmona_dsp.c119 u32 control_reg; local
152 control_reg = GML_CONVERTER_ENABLE | GML_48KHZ;
153 err = write_control_reg(chip, control_reg, TRUE);
200 u32 control_reg, clock; local
246 control_reg = le32_to_cpu(chip->comm_page->control_register);
247 control_reg &= GML_CLOCK_CLEAR_MASK;
248 control_reg &= GML_SPDIF_RATE_CLEAR_MASK;
263 if (control_reg & GML_SPDIF_PRO_MODE)
287 control_reg |= clock;
293 return write_control_reg(chip, control_reg, force_writ
300 u32 control_reg, clocks_from_dsp; local
369 u32 control_reg; local
[all...]
H A Dindigo_dsp.c100 u32 control_reg; local
104 control_reg = MIA_96000;
107 control_reg = MIA_88200;
110 control_reg = MIA_48000;
113 control_reg = MIA_44100;
116 control_reg = MIA_32000;
124 if (control_reg != le32_to_cpu(chip->comm_page->control_register)) {
129 chip->comm_page->control_register = cpu_to_le32(control_reg);
H A Dindigodj_dsp.c100 u32 control_reg; local
104 control_reg = MIA_96000;
107 control_reg = MIA_88200;
110 control_reg = MIA_48000;
113 control_reg = MIA_44100;
116 control_reg = MIA_32000;
124 if (control_reg != le32_to_cpu(chip->comm_page->control_register)) {
129 chip->comm_page->control_register = cpu_to_le32(control_reg);
H A Dmia_dsp.c117 u32 control_reg; local
121 control_reg = MIA_96000;
124 control_reg = MIA_88200;
127 control_reg = MIA_48000;
130 control_reg = MIA_44100;
133 control_reg = MIA_32000;
142 control_reg |= MIA_SPDIF;
145 if (control_reg != le32_to_cpu(chip->comm_page->control_register)) {
150 chip->comm_page->control_register = cpu_to_le32(control_reg);
H A Decho3g_dsp.c120 u32 control_reg = le32_to_cpu(chip->comm_page->control_register); local
123 control_reg |= E3G_PHANTOM_POWER;
125 control_reg &= ~E3G_PHANTOM_POWER;
128 return write_control_reg(chip, control_reg,
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/drivers/scsi/pcmcia/
H A Dnsp_message.c15 unsigned char data_reg, control_reg; local
27 control_reg = nsp_index_read(base, SCSIBUSCTRL);
28 control_reg |= SCSI_ACK;
29 nsp_index_write(base, SCSIBUSCTRL, control_reg);
35 control_reg = nsp_index_read(base, SCSIBUSCTRL);
36 control_reg &= ~SCSI_ACK;
37 nsp_index_write(base, SCSIBUSCTRL, control_reg);
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/drivers/sbus/char/
H A Dvfc_dev.c65 dev->control_reg |= VFC_CONTROL_CAPTRESET;
66 sbus_writel(dev->control_reg, &dev->regs->control);
67 dev->control_reg &= ~VFC_CONTROL_CAPTRESET;
68 sbus_writel(dev->control_reg, &dev->regs->control);
69 dev->control_reg |= VFC_CONTROL_CAPTRESET;
70 sbus_writel(dev->control_reg, &dev->regs->control);
75 dev->control_reg |= VFC_CONTROL_MEMPTR;
76 sbus_writel(dev->control_reg, &dev->regs->control);
77 dev->control_reg &= ~VFC_CONTROL_MEMPTR;
78 sbus_writel(dev->control_reg,
[all...]
H A Dvfc.h128 unsigned int control_reg; member in struct:vfc_dev
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/drivers/serial/
H A Dpmac_zilog.h55 volatile u8 __iomem *control_reg; member in struct:uart_pmac_port
84 writeb(reg, port->control_reg);
85 return readb(port->control_reg);
91 writeb(reg, port->control_reg);
92 writeb(value, port->control_reg);
107 (void)readb(port->control_reg);
H A Dpmac_zilog.c1390 uap->control_reg = uap->port.membase;
1391 uap->data_reg = uap->control_reg + 0x10;
1494 iounmap(uap->control_reg);
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/arch/powerpc/sysdev/qe_lib/
H A Dqe_ic.c466 u32 temp, control_reg = QEIC_CICNR, shift = 0; local
486 control_reg = QEIC_CRICR;
490 control_reg = QEIC_CRICR;
497 temp = qe_ic_read(qe_ic->regs, control_reg);
500 qe_ic_write(qe_ic->regs, control_reg, temp);

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