1/* 2 * linux/drivers/serial/pmac_zilog.c 3 * 4 * Driver for PowerMac Z85c30 based ESCC cell found in the 5 * "macio" ASICs of various PowerMac models 6 * 7 * Copyright (C) 2003 Ben. Herrenschmidt (benh@kernel.crashing.org) 8 * 9 * Derived from drivers/macintosh/macserial.c by Paul Mackerras 10 * and drivers/serial/sunzilog.c by David S. Miller 11 * 12 * Hrm... actually, I ripped most of sunzilog (Thanks David !) and 13 * adapted special tweaks needed for us. I don't think it's worth 14 * merging back those though. The DMA code still has to get in 15 * and once done, I expect that driver to remain fairly stable in 16 * the long term, unless we change the driver model again... 17 * 18 * This program is free software; you can redistribute it and/or modify 19 * it under the terms of the GNU General Public License as published by 20 * the Free Software Foundation; either version 2 of the License, or 21 * (at your option) any later version. 22 * 23 * This program is distributed in the hope that it will be useful, 24 * but WITHOUT ANY WARRANTY; without even the implied warranty of 25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 26 * GNU General Public License for more details. 27 * 28 * You should have received a copy of the GNU General Public License 29 * along with this program; if not, write to the Free Software 30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 31 * 32 * 2004-08-06 Harald Welte <laforge@gnumonks.org> 33 * - Enable BREAK interrupt 34 * - Add support for sysreq 35 * 36 * TODO: - Add DMA support 37 * - Defer port shutdown to a few seconds after close 38 * - maybe put something right into uap->clk_divisor 39 */ 40 41#undef DEBUG 42#undef DEBUG_HARD 43#undef USE_CTRL_O_SYSRQ 44 45#include <linux/module.h> 46#include <linux/tty.h> 47 48#include <linux/tty_flip.h> 49#include <linux/major.h> 50#include <linux/string.h> 51#include <linux/fcntl.h> 52#include <linux/mm.h> 53#include <linux/kernel.h> 54#include <linux/delay.h> 55#include <linux/init.h> 56#include <linux/console.h> 57#include <linux/slab.h> 58#include <linux/adb.h> 59#include <linux/pmu.h> 60#include <linux/bitops.h> 61#include <linux/sysrq.h> 62#include <linux/mutex.h> 63#include <asm/sections.h> 64#include <asm/io.h> 65#include <asm/irq.h> 66#include <asm/prom.h> 67#include <asm/machdep.h> 68#include <asm/pmac_feature.h> 69#include <asm/dbdma.h> 70#include <asm/macio.h> 71 72#if defined(CONFIG_SERIAL_PMACZILOG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 73#define SUPPORT_SYSRQ 74#endif 75 76#include <linux/serial.h> 77#include <linux/serial_core.h> 78 79#include "pmac_zilog.h" 80 81/* Not yet implemented */ 82#undef HAS_DBDMA 83 84static char version[] __initdata = "pmac_zilog: 0.6 (Benjamin Herrenschmidt <benh@kernel.crashing.org>)"; 85MODULE_AUTHOR("Benjamin Herrenschmidt <benh@kernel.crashing.org>"); 86MODULE_DESCRIPTION("Driver for the PowerMac serial ports."); 87MODULE_LICENSE("GPL"); 88 89#define PWRDBG(fmt, arg...) printk(KERN_DEBUG fmt , ## arg) 90 91 92/* 93 * For the sake of early serial console, we can do a pre-probe 94 * (optional) of the ports at rather early boot time. 95 */ 96static struct uart_pmac_port pmz_ports[MAX_ZS_PORTS]; 97static int pmz_ports_count; 98static DEFINE_MUTEX(pmz_irq_mutex); 99 100static struct uart_driver pmz_uart_reg = { 101 .owner = THIS_MODULE, 102 .driver_name = "ttyS", 103 .dev_name = "ttyS", 104 .major = TTY_MAJOR, 105}; 106 107 108/* 109 * Load all registers to reprogram the port 110 * This function must only be called when the TX is not busy. The UART 111 * port lock must be held and local interrupts disabled. 112 */ 113static void pmz_load_zsregs(struct uart_pmac_port *uap, u8 *regs) 114{ 115 int i; 116 117 if (ZS_IS_ASLEEP(uap)) 118 return; 119 120 /* Let pending transmits finish. */ 121 for (i = 0; i < 1000; i++) { 122 unsigned char stat = read_zsreg(uap, R1); 123 if (stat & ALL_SNT) 124 break; 125 udelay(100); 126 } 127 128 ZS_CLEARERR(uap); 129 zssync(uap); 130 ZS_CLEARFIFO(uap); 131 zssync(uap); 132 ZS_CLEARERR(uap); 133 134 /* Disable all interrupts. */ 135 write_zsreg(uap, R1, 136 regs[R1] & ~(RxINT_MASK | TxINT_ENAB | EXT_INT_ENAB)); 137 138 /* Set parity, sync config, stop bits, and clock divisor. */ 139 write_zsreg(uap, R4, regs[R4]); 140 141 /* Set misc. TX/RX control bits. */ 142 write_zsreg(uap, R10, regs[R10]); 143 144 /* Set TX/RX controls sans the enable bits. */ 145 write_zsreg(uap, R3, regs[R3] & ~RxENABLE); 146 write_zsreg(uap, R5, regs[R5] & ~TxENABLE); 147 148 /* now set R7 "prime" on ESCC */ 149 write_zsreg(uap, R15, regs[R15] | EN85C30); 150 write_zsreg(uap, R7, regs[R7P]); 151 152 /* make sure we use R7 "non-prime" on ESCC */ 153 write_zsreg(uap, R15, regs[R15] & ~EN85C30); 154 155 /* Synchronous mode config. */ 156 write_zsreg(uap, R6, regs[R6]); 157 write_zsreg(uap, R7, regs[R7]); 158 159 /* Disable baud generator. */ 160 write_zsreg(uap, R14, regs[R14] & ~BRENAB); 161 162 /* Clock mode control. */ 163 write_zsreg(uap, R11, regs[R11]); 164 165 /* Lower and upper byte of baud rate generator divisor. */ 166 write_zsreg(uap, R12, regs[R12]); 167 write_zsreg(uap, R13, regs[R13]); 168 169 /* Now rewrite R14, with BRENAB (if set). */ 170 write_zsreg(uap, R14, regs[R14]); 171 172 /* Reset external status interrupts. */ 173 write_zsreg(uap, R0, RES_EXT_INT); 174 write_zsreg(uap, R0, RES_EXT_INT); 175 176 /* Rewrite R3/R5, this time without enables masked. */ 177 write_zsreg(uap, R3, regs[R3]); 178 write_zsreg(uap, R5, regs[R5]); 179 180 /* Rewrite R1, this time without IRQ enabled masked. */ 181 write_zsreg(uap, R1, regs[R1]); 182 183 /* Enable interrupts */ 184 write_zsreg(uap, R9, regs[R9]); 185} 186 187/* 188 * We do like sunzilog to avoid disrupting pending Tx 189 * Reprogram the Zilog channel HW registers with the copies found in the 190 * software state struct. If the transmitter is busy, we defer this update 191 * until the next TX complete interrupt. Else, we do it right now. 192 * 193 * The UART port lock must be held and local interrupts disabled. 194 */ 195static void pmz_maybe_update_regs(struct uart_pmac_port *uap) 196{ 197 if (!ZS_REGS_HELD(uap)) { 198 if (ZS_TX_ACTIVE(uap)) { 199 uap->flags |= PMACZILOG_FLAG_REGS_HELD; 200 } else { 201 pmz_debug("pmz: maybe_update_regs: updating\n"); 202 pmz_load_zsregs(uap, uap->curregs); 203 } 204 } 205} 206 207static struct tty_struct *pmz_receive_chars(struct uart_pmac_port *uap) 208{ 209 struct tty_struct *tty = NULL; 210 unsigned char ch, r1, drop, error, flag; 211 int loops = 0; 212 213 /* The interrupt can be enabled when the port isn't open, typically 214 * that happens when using one port is open and the other closed (stale 215 * interrupt) or when one port is used as a console. 216 */ 217 if (!ZS_IS_OPEN(uap)) { 218 pmz_debug("pmz: draining input\n"); 219 /* Port is closed, drain input data */ 220 for (;;) { 221 if ((++loops) > 1000) 222 goto flood; 223 (void)read_zsreg(uap, R1); 224 write_zsreg(uap, R0, ERR_RES); 225 (void)read_zsdata(uap); 226 ch = read_zsreg(uap, R0); 227 if (!(ch & Rx_CH_AV)) 228 break; 229 } 230 return NULL; 231 } 232 233 /* Sanity check, make sure the old bug is no longer happening */ 234 if (uap->port.info == NULL || uap->port.info->tty == NULL) { 235 WARN_ON(1); 236 (void)read_zsdata(uap); 237 return NULL; 238 } 239 tty = uap->port.info->tty; 240 241 while (1) { 242 error = 0; 243 drop = 0; 244 245 r1 = read_zsreg(uap, R1); 246 ch = read_zsdata(uap); 247 248 if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR)) { 249 write_zsreg(uap, R0, ERR_RES); 250 zssync(uap); 251 } 252 253 ch &= uap->parity_mask; 254 if (ch == 0 && uap->flags & PMACZILOG_FLAG_BREAK) { 255 uap->flags &= ~PMACZILOG_FLAG_BREAK; 256 } 257 258#if defined(CONFIG_MAGIC_SYSRQ) && defined(CONFIG_SERIAL_CORE_CONSOLE) 259#ifdef USE_CTRL_O_SYSRQ 260 /* Handle the SysRq ^O Hack */ 261 if (ch == '\x0f') { 262 uap->port.sysrq = jiffies + HZ*5; 263 goto next_char; 264 } 265#endif /* USE_CTRL_O_SYSRQ */ 266 if (uap->port.sysrq) { 267 int swallow; 268 spin_unlock(&uap->port.lock); 269 swallow = uart_handle_sysrq_char(&uap->port, ch); 270 spin_lock(&uap->port.lock); 271 if (swallow) 272 goto next_char; 273 } 274#endif /* CONFIG_MAGIC_SYSRQ && CONFIG_SERIAL_CORE_CONSOLE */ 275 276 /* A real serial line, record the character and status. */ 277 if (drop) 278 goto next_char; 279 280 flag = TTY_NORMAL; 281 uap->port.icount.rx++; 282 283 if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR | BRK_ABRT)) { 284 error = 1; 285 if (r1 & BRK_ABRT) { 286 pmz_debug("pmz: got break !\n"); 287 r1 &= ~(PAR_ERR | CRC_ERR); 288 uap->port.icount.brk++; 289 if (uart_handle_break(&uap->port)) 290 goto next_char; 291 } 292 else if (r1 & PAR_ERR) 293 uap->port.icount.parity++; 294 else if (r1 & CRC_ERR) 295 uap->port.icount.frame++; 296 if (r1 & Rx_OVR) 297 uap->port.icount.overrun++; 298 r1 &= uap->port.read_status_mask; 299 if (r1 & BRK_ABRT) 300 flag = TTY_BREAK; 301 else if (r1 & PAR_ERR) 302 flag = TTY_PARITY; 303 else if (r1 & CRC_ERR) 304 flag = TTY_FRAME; 305 } 306 307 if (uap->port.ignore_status_mask == 0xff || 308 (r1 & uap->port.ignore_status_mask) == 0) { 309 tty_insert_flip_char(tty, ch, flag); 310 } 311 if (r1 & Rx_OVR) 312 tty_insert_flip_char(tty, 0, TTY_OVERRUN); 313 next_char: 314 /* We can get stuck in an infinite loop getting char 0 when the 315 * line is in a wrong HW state, we break that here. 316 * When that happens, I disable the receive side of the driver. 317 * Note that what I've been experiencing is a real irq loop where 318 * I'm getting flooded regardless of the actual port speed. 319 * Something stange is going on with the HW 320 */ 321 if ((++loops) > 1000) 322 goto flood; 323 ch = read_zsreg(uap, R0); 324 if (!(ch & Rx_CH_AV)) 325 break; 326 } 327 328 return tty; 329 flood: 330 uap->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK); 331 write_zsreg(uap, R1, uap->curregs[R1]); 332 zssync(uap); 333 dev_err(&uap->dev->ofdev.dev, "pmz: rx irq flood !\n"); 334 return tty; 335} 336 337static void pmz_status_handle(struct uart_pmac_port *uap) 338{ 339 unsigned char status; 340 341 status = read_zsreg(uap, R0); 342 write_zsreg(uap, R0, RES_EXT_INT); 343 zssync(uap); 344 345 if (ZS_IS_OPEN(uap) && ZS_WANTS_MODEM_STATUS(uap)) { 346 if (status & SYNC_HUNT) 347 uap->port.icount.dsr++; 348 349 /* The Zilog just gives us an interrupt when DCD/CTS/etc. change. 350 * But it does not tell us which bit has changed, we have to keep 351 * track of this ourselves. 352 * The CTS input is inverted for some reason. -- paulus 353 */ 354 if ((status ^ uap->prev_status) & DCD) 355 uart_handle_dcd_change(&uap->port, 356 (status & DCD)); 357 if ((status ^ uap->prev_status) & CTS) 358 uart_handle_cts_change(&uap->port, 359 !(status & CTS)); 360 361 wake_up_interruptible(&uap->port.info->delta_msr_wait); 362 } 363 364 if (status & BRK_ABRT) 365 uap->flags |= PMACZILOG_FLAG_BREAK; 366 367 uap->prev_status = status; 368} 369 370static void pmz_transmit_chars(struct uart_pmac_port *uap) 371{ 372 struct circ_buf *xmit; 373 374 if (ZS_IS_ASLEEP(uap)) 375 return; 376 if (ZS_IS_CONS(uap)) { 377 unsigned char status = read_zsreg(uap, R0); 378 379 /* TX still busy? Just wait for the next TX done interrupt. 380 * 381 * It can occur because of how we do serial console writes. It would 382 * be nice to transmit console writes just like we normally would for 383 * a TTY line. (ie. buffered and TX interrupt driven). That is not 384 * easy because console writes cannot sleep. One solution might be 385 * to poll on enough port->xmit space becomming free. -DaveM 386 */ 387 if (!(status & Tx_BUF_EMP)) 388 return; 389 } 390 391 uap->flags &= ~PMACZILOG_FLAG_TX_ACTIVE; 392 393 if (ZS_REGS_HELD(uap)) { 394 pmz_load_zsregs(uap, uap->curregs); 395 uap->flags &= ~PMACZILOG_FLAG_REGS_HELD; 396 } 397 398 if (ZS_TX_STOPPED(uap)) { 399 uap->flags &= ~PMACZILOG_FLAG_TX_STOPPED; 400 goto ack_tx_int; 401 } 402 403 if (uap->port.x_char) { 404 uap->flags |= PMACZILOG_FLAG_TX_ACTIVE; 405 write_zsdata(uap, uap->port.x_char); 406 zssync(uap); 407 uap->port.icount.tx++; 408 uap->port.x_char = 0; 409 return; 410 } 411 412 if (uap->port.info == NULL) 413 goto ack_tx_int; 414 xmit = &uap->port.info->xmit; 415 if (uart_circ_empty(xmit)) { 416 uart_write_wakeup(&uap->port); 417 goto ack_tx_int; 418 } 419 if (uart_tx_stopped(&uap->port)) 420 goto ack_tx_int; 421 422 uap->flags |= PMACZILOG_FLAG_TX_ACTIVE; 423 write_zsdata(uap, xmit->buf[xmit->tail]); 424 zssync(uap); 425 426 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 427 uap->port.icount.tx++; 428 429 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 430 uart_write_wakeup(&uap->port); 431 432 return; 433 434ack_tx_int: 435 write_zsreg(uap, R0, RES_Tx_P); 436 zssync(uap); 437} 438 439static irqreturn_t pmz_interrupt(int irq, void *dev_id) 440{ 441 struct uart_pmac_port *uap = dev_id; 442 struct uart_pmac_port *uap_a; 443 struct uart_pmac_port *uap_b; 444 int rc = IRQ_NONE; 445 struct tty_struct *tty; 446 u8 r3; 447 448 uap_a = pmz_get_port_A(uap); 449 uap_b = uap_a->mate; 450 451 spin_lock(&uap_a->port.lock); 452 r3 = read_zsreg(uap_a, R3); 453 454#ifdef DEBUG_HARD 455 pmz_debug("irq, r3: %x\n", r3); 456#endif 457 /* Channel A */ 458 tty = NULL; 459 if (r3 & (CHAEXT | CHATxIP | CHARxIP)) { 460 write_zsreg(uap_a, R0, RES_H_IUS); 461 zssync(uap_a); 462 if (r3 & CHAEXT) 463 pmz_status_handle(uap_a); 464 if (r3 & CHARxIP) 465 tty = pmz_receive_chars(uap_a); 466 if (r3 & CHATxIP) 467 pmz_transmit_chars(uap_a); 468 rc = IRQ_HANDLED; 469 } 470 spin_unlock(&uap_a->port.lock); 471 if (tty != NULL) 472 tty_flip_buffer_push(tty); 473 474 if (uap_b->node == NULL) 475 goto out; 476 477 spin_lock(&uap_b->port.lock); 478 tty = NULL; 479 if (r3 & (CHBEXT | CHBTxIP | CHBRxIP)) { 480 write_zsreg(uap_b, R0, RES_H_IUS); 481 zssync(uap_b); 482 if (r3 & CHBEXT) 483 pmz_status_handle(uap_b); 484 if (r3 & CHBRxIP) 485 tty = pmz_receive_chars(uap_b); 486 if (r3 & CHBTxIP) 487 pmz_transmit_chars(uap_b); 488 rc = IRQ_HANDLED; 489 } 490 spin_unlock(&uap_b->port.lock); 491 if (tty != NULL) 492 tty_flip_buffer_push(tty); 493 494 out: 495#ifdef DEBUG_HARD 496 pmz_debug("irq done.\n"); 497#endif 498 return rc; 499} 500 501/* 502 * Peek the status register, lock not held by caller 503 */ 504static inline u8 pmz_peek_status(struct uart_pmac_port *uap) 505{ 506 unsigned long flags; 507 u8 status; 508 509 spin_lock_irqsave(&uap->port.lock, flags); 510 status = read_zsreg(uap, R0); 511 spin_unlock_irqrestore(&uap->port.lock, flags); 512 513 return status; 514} 515 516/* 517 * Check if transmitter is empty 518 * The port lock is not held. 519 */ 520static unsigned int pmz_tx_empty(struct uart_port *port) 521{ 522 struct uart_pmac_port *uap = to_pmz(port); 523 unsigned char status; 524 525 if (ZS_IS_ASLEEP(uap) || uap->node == NULL) 526 return TIOCSER_TEMT; 527 528 status = pmz_peek_status(to_pmz(port)); 529 if (status & Tx_BUF_EMP) 530 return TIOCSER_TEMT; 531 return 0; 532} 533 534/* 535 * Set Modem Control (RTS & DTR) bits 536 * The port lock is held and interrupts are disabled. 537 * Note: Shall we really filter out RTS on external ports or 538 * should that be dealt at higher level only ? 539 */ 540static void pmz_set_mctrl(struct uart_port *port, unsigned int mctrl) 541{ 542 struct uart_pmac_port *uap = to_pmz(port); 543 unsigned char set_bits, clear_bits; 544 545 /* Do nothing for irda for now... */ 546 if (ZS_IS_IRDA(uap)) 547 return; 548 /* We get called during boot with a port not up yet */ 549 if (ZS_IS_ASLEEP(uap) || 550 !(ZS_IS_OPEN(uap) || ZS_IS_CONS(uap))) 551 return; 552 553 set_bits = clear_bits = 0; 554 555 if (ZS_IS_INTMODEM(uap)) { 556 if (mctrl & TIOCM_RTS) 557 set_bits |= RTS; 558 else 559 clear_bits |= RTS; 560 } 561 if (mctrl & TIOCM_DTR) 562 set_bits |= DTR; 563 else 564 clear_bits |= DTR; 565 566 /* NOTE: Not subject to 'transmitter active' rule. */ 567 uap->curregs[R5] |= set_bits; 568 uap->curregs[R5] &= ~clear_bits; 569 if (ZS_IS_ASLEEP(uap)) 570 return; 571 write_zsreg(uap, R5, uap->curregs[R5]); 572 pmz_debug("pmz_set_mctrl: set bits: %x, clear bits: %x -> %x\n", 573 set_bits, clear_bits, uap->curregs[R5]); 574 zssync(uap); 575} 576 577/* 578 * Get Modem Control bits (only the input ones, the core will 579 * or that with a cached value of the control ones) 580 * The port lock is held and interrupts are disabled. 581 */ 582static unsigned int pmz_get_mctrl(struct uart_port *port) 583{ 584 struct uart_pmac_port *uap = to_pmz(port); 585 unsigned char status; 586 unsigned int ret; 587 588 if (ZS_IS_ASLEEP(uap) || uap->node == NULL) 589 return 0; 590 591 status = read_zsreg(uap, R0); 592 593 ret = 0; 594 if (status & DCD) 595 ret |= TIOCM_CAR; 596 if (status & SYNC_HUNT) 597 ret |= TIOCM_DSR; 598 if (!(status & CTS)) 599 ret |= TIOCM_CTS; 600 601 return ret; 602} 603 604/* 605 * Stop TX side. Dealt like sunzilog at next Tx interrupt, 606 * though for DMA, we will have to do a bit more. 607 * The port lock is held and interrupts are disabled. 608 */ 609static void pmz_stop_tx(struct uart_port *port) 610{ 611 to_pmz(port)->flags |= PMACZILOG_FLAG_TX_STOPPED; 612} 613 614/* 615 * Kick the Tx side. 616 * The port lock is held and interrupts are disabled. 617 */ 618static void pmz_start_tx(struct uart_port *port) 619{ 620 struct uart_pmac_port *uap = to_pmz(port); 621 unsigned char status; 622 623 pmz_debug("pmz: start_tx()\n"); 624 625 uap->flags |= PMACZILOG_FLAG_TX_ACTIVE; 626 uap->flags &= ~PMACZILOG_FLAG_TX_STOPPED; 627 628 if (ZS_IS_ASLEEP(uap) || uap->node == NULL) 629 return; 630 631 status = read_zsreg(uap, R0); 632 633 /* TX busy? Just wait for the TX done interrupt. */ 634 if (!(status & Tx_BUF_EMP)) 635 return; 636 637 /* Send the first character to jump-start the TX done 638 * IRQ sending engine. 639 */ 640 if (port->x_char) { 641 write_zsdata(uap, port->x_char); 642 zssync(uap); 643 port->icount.tx++; 644 port->x_char = 0; 645 } else { 646 struct circ_buf *xmit = &port->info->xmit; 647 648 write_zsdata(uap, xmit->buf[xmit->tail]); 649 zssync(uap); 650 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 651 port->icount.tx++; 652 653 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 654 uart_write_wakeup(&uap->port); 655 } 656 pmz_debug("pmz: start_tx() done.\n"); 657} 658 659/* 660 * Stop Rx side, basically disable emitting of 661 * Rx interrupts on the port. We don't disable the rx 662 * side of the chip proper though 663 * The port lock is held. 664 */ 665static void pmz_stop_rx(struct uart_port *port) 666{ 667 struct uart_pmac_port *uap = to_pmz(port); 668 669 if (ZS_IS_ASLEEP(uap) || uap->node == NULL) 670 return; 671 672 pmz_debug("pmz: stop_rx()()\n"); 673 674 /* Disable all RX interrupts. */ 675 uap->curregs[R1] &= ~RxINT_MASK; 676 pmz_maybe_update_regs(uap); 677 678 pmz_debug("pmz: stop_rx() done.\n"); 679} 680 681/* 682 * Enable modem status change interrupts 683 * The port lock is held. 684 */ 685static void pmz_enable_ms(struct uart_port *port) 686{ 687 struct uart_pmac_port *uap = to_pmz(port); 688 unsigned char new_reg; 689 690 if (ZS_IS_IRDA(uap) || uap->node == NULL) 691 return; 692 new_reg = uap->curregs[R15] | (DCDIE | SYNCIE | CTSIE); 693 if (new_reg != uap->curregs[R15]) { 694 uap->curregs[R15] = new_reg; 695 696 if (ZS_IS_ASLEEP(uap)) 697 return; 698 /* NOTE: Not subject to 'transmitter active' rule. */ 699 write_zsreg(uap, R15, uap->curregs[R15]); 700 } 701} 702 703/* 704 * Control break state emission 705 * The port lock is not held. 706 */ 707static void pmz_break_ctl(struct uart_port *port, int break_state) 708{ 709 struct uart_pmac_port *uap = to_pmz(port); 710 unsigned char set_bits, clear_bits, new_reg; 711 unsigned long flags; 712 713 if (uap->node == NULL) 714 return; 715 set_bits = clear_bits = 0; 716 717 if (break_state) 718 set_bits |= SND_BRK; 719 else 720 clear_bits |= SND_BRK; 721 722 spin_lock_irqsave(&port->lock, flags); 723 724 new_reg = (uap->curregs[R5] | set_bits) & ~clear_bits; 725 if (new_reg != uap->curregs[R5]) { 726 uap->curregs[R5] = new_reg; 727 728 /* NOTE: Not subject to 'transmitter active' rule. */ 729 if (ZS_IS_ASLEEP(uap)) 730 return; 731 write_zsreg(uap, R5, uap->curregs[R5]); 732 } 733 734 spin_unlock_irqrestore(&port->lock, flags); 735} 736 737/* 738 * Turn power on or off to the SCC and associated stuff 739 * (port drivers, modem, IR port, etc.) 740 * Returns the number of milliseconds we should wait before 741 * trying to use the port. 742 */ 743static int pmz_set_scc_power(struct uart_pmac_port *uap, int state) 744{ 745 int delay = 0; 746 int rc; 747 748 if (state) { 749 rc = pmac_call_feature( 750 PMAC_FTR_SCC_ENABLE, uap->node, uap->port_type, 1); 751 pmz_debug("port power on result: %d\n", rc); 752 if (ZS_IS_INTMODEM(uap)) { 753 rc = pmac_call_feature( 754 PMAC_FTR_MODEM_ENABLE, uap->node, 0, 1); 755 delay = 2500; /* wait for 2.5s before using */ 756 pmz_debug("modem power result: %d\n", rc); 757 } 758 } else { 759 /* TODO: Make that depend on a timer, don't power down 760 * immediately 761 */ 762 if (ZS_IS_INTMODEM(uap)) { 763 rc = pmac_call_feature( 764 PMAC_FTR_MODEM_ENABLE, uap->node, 0, 0); 765 pmz_debug("port power off result: %d\n", rc); 766 } 767 pmac_call_feature(PMAC_FTR_SCC_ENABLE, uap->node, uap->port_type, 0); 768 } 769 return delay; 770} 771 772static void pmz_fix_zero_bug_scc(struct uart_pmac_port *uap) 773{ 774 write_zsreg(uap, 9, ZS_IS_CHANNEL_A(uap) ? CHRA : CHRB); 775 zssync(uap); 776 udelay(10); 777 write_zsreg(uap, 9, (ZS_IS_CHANNEL_A(uap) ? CHRA : CHRB) | NV); 778 zssync(uap); 779 780 write_zsreg(uap, 4, X1CLK | MONSYNC); 781 write_zsreg(uap, 3, Rx8); 782 write_zsreg(uap, 5, Tx8 | RTS); 783 write_zsreg(uap, 9, NV); /* Didn't we already do this? */ 784 write_zsreg(uap, 11, RCBR | TCBR); 785 write_zsreg(uap, 12, 0); 786 write_zsreg(uap, 13, 0); 787 write_zsreg(uap, 14, (LOOPBAK | BRSRC)); 788 write_zsreg(uap, 14, (LOOPBAK | BRSRC | BRENAB)); 789 write_zsreg(uap, 3, Rx8 | RxENABLE); 790 write_zsreg(uap, 0, RES_EXT_INT); 791 write_zsreg(uap, 0, RES_EXT_INT); 792 write_zsreg(uap, 0, RES_EXT_INT); /* to kill some time */ 793 794 /* The channel should be OK now, but it is probably receiving 795 * loopback garbage. 796 * Switch to asynchronous mode, disable the receiver, 797 * and discard everything in the receive buffer. 798 */ 799 write_zsreg(uap, 9, NV); 800 write_zsreg(uap, 4, X16CLK | SB_MASK); 801 write_zsreg(uap, 3, Rx8); 802 803 while (read_zsreg(uap, 0) & Rx_CH_AV) { 804 (void)read_zsreg(uap, 8); 805 write_zsreg(uap, 0, RES_EXT_INT); 806 write_zsreg(uap, 0, ERR_RES); 807 } 808} 809 810/* 811 * Real startup routine, powers up the hardware and sets up 812 * the SCC. Returns a delay in ms where you need to wait before 813 * actually using the port, this is typically the internal modem 814 * powerup delay. This routine expect the lock to be taken. 815 */ 816static int __pmz_startup(struct uart_pmac_port *uap) 817{ 818 int pwr_delay = 0; 819 820 memset(&uap->curregs, 0, sizeof(uap->curregs)); 821 822 /* Power up the SCC & underlying hardware (modem/irda) */ 823 pwr_delay = pmz_set_scc_power(uap, 1); 824 825 /* Nice buggy HW ... */ 826 pmz_fix_zero_bug_scc(uap); 827 828 /* Reset the channel */ 829 uap->curregs[R9] = 0; 830 write_zsreg(uap, 9, ZS_IS_CHANNEL_A(uap) ? CHRA : CHRB); 831 zssync(uap); 832 udelay(10); 833 write_zsreg(uap, 9, 0); 834 zssync(uap); 835 836 /* Clear the interrupt registers */ 837 write_zsreg(uap, R1, 0); 838 write_zsreg(uap, R0, ERR_RES); 839 write_zsreg(uap, R0, ERR_RES); 840 write_zsreg(uap, R0, RES_H_IUS); 841 write_zsreg(uap, R0, RES_H_IUS); 842 843 /* Setup some valid baud rate */ 844 uap->curregs[R4] = X16CLK | SB1; 845 uap->curregs[R3] = Rx8; 846 uap->curregs[R5] = Tx8 | RTS; 847 if (!ZS_IS_IRDA(uap)) 848 uap->curregs[R5] |= DTR; 849 uap->curregs[R12] = 0; 850 uap->curregs[R13] = 0; 851 uap->curregs[R14] = BRENAB; 852 853 /* Clear handshaking, enable BREAK interrupts */ 854 uap->curregs[R15] = BRKIE; 855 856 /* Master interrupt enable */ 857 uap->curregs[R9] |= NV | MIE; 858 859 pmz_load_zsregs(uap, uap->curregs); 860 861 /* Enable receiver and transmitter. */ 862 write_zsreg(uap, R3, uap->curregs[R3] |= RxENABLE); 863 write_zsreg(uap, R5, uap->curregs[R5] |= TxENABLE); 864 865 /* Remember status for DCD/CTS changes */ 866 uap->prev_status = read_zsreg(uap, R0); 867 868 869 return pwr_delay; 870} 871 872static void pmz_irda_reset(struct uart_pmac_port *uap) 873{ 874 uap->curregs[R5] |= DTR; 875 write_zsreg(uap, R5, uap->curregs[R5]); 876 zssync(uap); 877 mdelay(110); 878 uap->curregs[R5] &= ~DTR; 879 write_zsreg(uap, R5, uap->curregs[R5]); 880 zssync(uap); 881 mdelay(10); 882} 883 884/* 885 * This is the "normal" startup routine, using the above one 886 * wrapped with the lock and doing a schedule delay 887 */ 888static int pmz_startup(struct uart_port *port) 889{ 890 struct uart_pmac_port *uap = to_pmz(port); 891 unsigned long flags; 892 int pwr_delay = 0; 893 894 pmz_debug("pmz: startup()\n"); 895 896 if (ZS_IS_ASLEEP(uap)) 897 return -EAGAIN; 898 if (uap->node == NULL) 899 return -ENODEV; 900 901 mutex_lock(&pmz_irq_mutex); 902 903 uap->flags |= PMACZILOG_FLAG_IS_OPEN; 904 905 /* A console is never powered down. Else, power up and 906 * initialize the chip 907 */ 908 if (!ZS_IS_CONS(uap)) { 909 spin_lock_irqsave(&port->lock, flags); 910 pwr_delay = __pmz_startup(uap); 911 spin_unlock_irqrestore(&port->lock, flags); 912 } 913 914 pmz_get_port_A(uap)->flags |= PMACZILOG_FLAG_IS_IRQ_ON; 915 if (request_irq(uap->port.irq, pmz_interrupt, IRQF_SHARED, "PowerMac Zilog", uap)) { 916 dev_err(&uap->dev->ofdev.dev, 917 "Unable to register zs interrupt handler.\n"); 918 pmz_set_scc_power(uap, 0); 919 mutex_unlock(&pmz_irq_mutex); 920 return -ENXIO; 921 } 922 923 mutex_unlock(&pmz_irq_mutex); 924 925 /* Right now, we deal with delay by blocking here, I'll be 926 * smarter later on 927 */ 928 if (pwr_delay != 0) { 929 pmz_debug("pmz: delaying %d ms\n", pwr_delay); 930 msleep(pwr_delay); 931 } 932 933 /* IrDA reset is done now */ 934 if (ZS_IS_IRDA(uap)) 935 pmz_irda_reset(uap); 936 937 /* Enable interrupts emission from the chip */ 938 spin_lock_irqsave(&port->lock, flags); 939 uap->curregs[R1] |= INT_ALL_Rx | TxINT_ENAB; 940 if (!ZS_IS_EXTCLK(uap)) 941 uap->curregs[R1] |= EXT_INT_ENAB; 942 write_zsreg(uap, R1, uap->curregs[R1]); 943 spin_unlock_irqrestore(&port->lock, flags); 944 945 pmz_debug("pmz: startup() done.\n"); 946 947 return 0; 948} 949 950static void pmz_shutdown(struct uart_port *port) 951{ 952 struct uart_pmac_port *uap = to_pmz(port); 953 unsigned long flags; 954 955 pmz_debug("pmz: shutdown()\n"); 956 957 if (uap->node == NULL) 958 return; 959 960 mutex_lock(&pmz_irq_mutex); 961 962 /* Release interrupt handler */ 963 free_irq(uap->port.irq, uap); 964 965 spin_lock_irqsave(&port->lock, flags); 966 967 uap->flags &= ~PMACZILOG_FLAG_IS_OPEN; 968 969 if (!ZS_IS_OPEN(uap->mate)) 970 pmz_get_port_A(uap)->flags &= ~PMACZILOG_FLAG_IS_IRQ_ON; 971 972 /* Disable interrupts */ 973 if (!ZS_IS_ASLEEP(uap)) { 974 uap->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK); 975 write_zsreg(uap, R1, uap->curregs[R1]); 976 zssync(uap); 977 } 978 979 if (ZS_IS_CONS(uap) || ZS_IS_ASLEEP(uap)) { 980 spin_unlock_irqrestore(&port->lock, flags); 981 mutex_unlock(&pmz_irq_mutex); 982 return; 983 } 984 985 /* Disable receiver and transmitter. */ 986 uap->curregs[R3] &= ~RxENABLE; 987 uap->curregs[R5] &= ~TxENABLE; 988 989 /* Disable all interrupts and BRK assertion. */ 990 uap->curregs[R5] &= ~SND_BRK; 991 pmz_maybe_update_regs(uap); 992 993 /* Shut the chip down */ 994 pmz_set_scc_power(uap, 0); 995 996 spin_unlock_irqrestore(&port->lock, flags); 997 998 mutex_unlock(&pmz_irq_mutex); 999 1000 pmz_debug("pmz: shutdown() done.\n"); 1001} 1002 1003/* Shared by TTY driver and serial console setup. The port lock is held 1004 * and local interrupts are disabled. 1005 */ 1006static void pmz_convert_to_zs(struct uart_pmac_port *uap, unsigned int cflag, 1007 unsigned int iflag, unsigned long baud) 1008{ 1009 int brg; 1010 1011 1012 /* Switch to external clocking for IrDA high clock rates. That 1013 * code could be re-used for Midi interfaces with different 1014 * multipliers 1015 */ 1016 if (baud >= 115200 && ZS_IS_IRDA(uap)) { 1017 uap->curregs[R4] = X1CLK; 1018 uap->curregs[R11] = RCTRxCP | TCTRxCP; 1019 uap->curregs[R14] = 0; /* BRG off */ 1020 uap->curregs[R12] = 0; 1021 uap->curregs[R13] = 0; 1022 uap->flags |= PMACZILOG_FLAG_IS_EXTCLK; 1023 } else { 1024 switch (baud) { 1025 case ZS_CLOCK/16: /* 230400 */ 1026 uap->curregs[R4] = X16CLK; 1027 uap->curregs[R11] = 0; 1028 uap->curregs[R14] = 0; 1029 break; 1030 case ZS_CLOCK/32: /* 115200 */ 1031 uap->curregs[R4] = X32CLK; 1032 uap->curregs[R11] = 0; 1033 uap->curregs[R14] = 0; 1034 break; 1035 default: 1036 uap->curregs[R4] = X16CLK; 1037 uap->curregs[R11] = TCBR | RCBR; 1038 brg = BPS_TO_BRG(baud, ZS_CLOCK / 16); 1039 uap->curregs[R12] = (brg & 255); 1040 uap->curregs[R13] = ((brg >> 8) & 255); 1041 uap->curregs[R14] = BRENAB; 1042 } 1043 uap->flags &= ~PMACZILOG_FLAG_IS_EXTCLK; 1044 } 1045 1046 /* Character size, stop bits, and parity. */ 1047 uap->curregs[3] &= ~RxN_MASK; 1048 uap->curregs[5] &= ~TxN_MASK; 1049 1050 switch (cflag & CSIZE) { 1051 case CS5: 1052 uap->curregs[3] |= Rx5; 1053 uap->curregs[5] |= Tx5; 1054 uap->parity_mask = 0x1f; 1055 break; 1056 case CS6: 1057 uap->curregs[3] |= Rx6; 1058 uap->curregs[5] |= Tx6; 1059 uap->parity_mask = 0x3f; 1060 break; 1061 case CS7: 1062 uap->curregs[3] |= Rx7; 1063 uap->curregs[5] |= Tx7; 1064 uap->parity_mask = 0x7f; 1065 break; 1066 case CS8: 1067 default: 1068 uap->curregs[3] |= Rx8; 1069 uap->curregs[5] |= Tx8; 1070 uap->parity_mask = 0xff; 1071 break; 1072 }; 1073 uap->curregs[4] &= ~(SB_MASK); 1074 if (cflag & CSTOPB) 1075 uap->curregs[4] |= SB2; 1076 else 1077 uap->curregs[4] |= SB1; 1078 if (cflag & PARENB) 1079 uap->curregs[4] |= PAR_ENAB; 1080 else 1081 uap->curregs[4] &= ~PAR_ENAB; 1082 if (!(cflag & PARODD)) 1083 uap->curregs[4] |= PAR_EVEN; 1084 else 1085 uap->curregs[4] &= ~PAR_EVEN; 1086 1087 uap->port.read_status_mask = Rx_OVR; 1088 if (iflag & INPCK) 1089 uap->port.read_status_mask |= CRC_ERR | PAR_ERR; 1090 if (iflag & (BRKINT | PARMRK)) 1091 uap->port.read_status_mask |= BRK_ABRT; 1092 1093 uap->port.ignore_status_mask = 0; 1094 if (iflag & IGNPAR) 1095 uap->port.ignore_status_mask |= CRC_ERR | PAR_ERR; 1096 if (iflag & IGNBRK) { 1097 uap->port.ignore_status_mask |= BRK_ABRT; 1098 if (iflag & IGNPAR) 1099 uap->port.ignore_status_mask |= Rx_OVR; 1100 } 1101 1102 if ((cflag & CREAD) == 0) 1103 uap->port.ignore_status_mask = 0xff; 1104} 1105 1106 1107/* 1108 * Set the irda codec on the imac to the specified baud rate. 1109 */ 1110static void pmz_irda_setup(struct uart_pmac_port *uap, unsigned long *baud) 1111{ 1112 u8 cmdbyte; 1113 int t, version; 1114 1115 switch (*baud) { 1116 /* SIR modes */ 1117 case 2400: 1118 cmdbyte = 0x53; 1119 break; 1120 case 4800: 1121 cmdbyte = 0x52; 1122 break; 1123 case 9600: 1124 cmdbyte = 0x51; 1125 break; 1126 case 19200: 1127 cmdbyte = 0x50; 1128 break; 1129 case 38400: 1130 cmdbyte = 0x4f; 1131 break; 1132 case 57600: 1133 cmdbyte = 0x4e; 1134 break; 1135 case 115200: 1136 cmdbyte = 0x4d; 1137 break; 1138 /* The FIR modes aren't really supported at this point, how 1139 * do we select the speed ? via the FCR on KeyLargo ? 1140 */ 1141 case 1152000: 1142 cmdbyte = 0; 1143 break; 1144 case 4000000: 1145 cmdbyte = 0; 1146 break; 1147 default: /* 9600 */ 1148 cmdbyte = 0x51; 1149 *baud = 9600; 1150 break; 1151 } 1152 1153 /* Wait for transmitter to drain */ 1154 t = 10000; 1155 while ((read_zsreg(uap, R0) & Tx_BUF_EMP) == 0 1156 || (read_zsreg(uap, R1) & ALL_SNT) == 0) { 1157 if (--t <= 0) { 1158 dev_err(&uap->dev->ofdev.dev, "transmitter didn't drain\n"); 1159 return; 1160 } 1161 udelay(10); 1162 } 1163 1164 /* Drain the receiver too */ 1165 t = 100; 1166 (void)read_zsdata(uap); 1167 (void)read_zsdata(uap); 1168 (void)read_zsdata(uap); 1169 mdelay(10); 1170 while (read_zsreg(uap, R0) & Rx_CH_AV) { 1171 read_zsdata(uap); 1172 mdelay(10); 1173 if (--t <= 0) { 1174 dev_err(&uap->dev->ofdev.dev, "receiver didn't drain\n"); 1175 return; 1176 } 1177 } 1178 1179 /* Switch to command mode */ 1180 uap->curregs[R5] |= DTR; 1181 write_zsreg(uap, R5, uap->curregs[R5]); 1182 zssync(uap); 1183 mdelay(1); 1184 1185 /* Switch SCC to 19200 */ 1186 pmz_convert_to_zs(uap, CS8, 0, 19200); 1187 pmz_load_zsregs(uap, uap->curregs); 1188 mdelay(1); 1189 1190 /* Write get_version command byte */ 1191 write_zsdata(uap, 1); 1192 t = 5000; 1193 while ((read_zsreg(uap, R0) & Rx_CH_AV) == 0) { 1194 if (--t <= 0) { 1195 dev_err(&uap->dev->ofdev.dev, 1196 "irda_setup timed out on get_version byte\n"); 1197 goto out; 1198 } 1199 udelay(10); 1200 } 1201 version = read_zsdata(uap); 1202 1203 if (version < 4) { 1204 dev_info(&uap->dev->ofdev.dev, "IrDA: dongle version %d not supported\n", 1205 version); 1206 goto out; 1207 } 1208 1209 /* Send speed mode */ 1210 write_zsdata(uap, cmdbyte); 1211 t = 5000; 1212 while ((read_zsreg(uap, R0) & Rx_CH_AV) == 0) { 1213 if (--t <= 0) { 1214 dev_err(&uap->dev->ofdev.dev, 1215 "irda_setup timed out on speed mode byte\n"); 1216 goto out; 1217 } 1218 udelay(10); 1219 } 1220 t = read_zsdata(uap); 1221 if (t != cmdbyte) 1222 dev_err(&uap->dev->ofdev.dev, 1223 "irda_setup speed mode byte = %x (%x)\n", t, cmdbyte); 1224 1225 dev_info(&uap->dev->ofdev.dev, "IrDA setup for %ld bps, dongle version: %d\n", 1226 *baud, version); 1227 1228 (void)read_zsdata(uap); 1229 (void)read_zsdata(uap); 1230 (void)read_zsdata(uap); 1231 1232 out: 1233 /* Switch back to data mode */ 1234 uap->curregs[R5] &= ~DTR; 1235 write_zsreg(uap, R5, uap->curregs[R5]); 1236 zssync(uap); 1237 1238 (void)read_zsdata(uap); 1239 (void)read_zsdata(uap); 1240 (void)read_zsdata(uap); 1241} 1242 1243 1244static void __pmz_set_termios(struct uart_port *port, struct ktermios *termios, 1245 struct ktermios *old) 1246{ 1247 struct uart_pmac_port *uap = to_pmz(port); 1248 unsigned long baud; 1249 1250 pmz_debug("pmz: set_termios()\n"); 1251 1252 if (ZS_IS_ASLEEP(uap)) 1253 return; 1254 1255 memcpy(&uap->termios_cache, termios, sizeof(struct ktermios)); 1256 1257 if (ZS_IS_IRDA(uap)) { 1258 /* Calc baud rate */ 1259 baud = uart_get_baud_rate(port, termios, old, 1200, 4000000); 1260 pmz_debug("pmz: switch IRDA to %ld bauds\n", baud); 1261 /* Cet the irda codec to the right rate */ 1262 pmz_irda_setup(uap, &baud); 1263 /* Set final baud rate */ 1264 pmz_convert_to_zs(uap, termios->c_cflag, termios->c_iflag, baud); 1265 pmz_load_zsregs(uap, uap->curregs); 1266 zssync(uap); 1267 } else { 1268 baud = uart_get_baud_rate(port, termios, old, 1200, 230400); 1269 pmz_convert_to_zs(uap, termios->c_cflag, termios->c_iflag, baud); 1270 /* Make sure modem status interrupts are correctly configured */ 1271 if (UART_ENABLE_MS(&uap->port, termios->c_cflag)) { 1272 uap->curregs[R15] |= DCDIE | SYNCIE | CTSIE; 1273 uap->flags |= PMACZILOG_FLAG_MODEM_STATUS; 1274 } else { 1275 uap->curregs[R15] &= ~(DCDIE | SYNCIE | CTSIE); 1276 uap->flags &= ~PMACZILOG_FLAG_MODEM_STATUS; 1277 } 1278 1279 /* Load registers to the chip */ 1280 pmz_maybe_update_regs(uap); 1281 } 1282 uart_update_timeout(port, termios->c_cflag, baud); 1283 1284 pmz_debug("pmz: set_termios() done.\n"); 1285} 1286 1287/* The port lock is not held. */ 1288static void pmz_set_termios(struct uart_port *port, struct ktermios *termios, 1289 struct ktermios *old) 1290{ 1291 struct uart_pmac_port *uap = to_pmz(port); 1292 unsigned long flags; 1293 1294 spin_lock_irqsave(&port->lock, flags); 1295 1296 /* Disable IRQs on the port */ 1297 uap->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK); 1298 write_zsreg(uap, R1, uap->curregs[R1]); 1299 1300 /* Setup new port configuration */ 1301 __pmz_set_termios(port, termios, old); 1302 1303 /* Re-enable IRQs on the port */ 1304 if (ZS_IS_OPEN(uap)) { 1305 uap->curregs[R1] |= INT_ALL_Rx | TxINT_ENAB; 1306 if (!ZS_IS_EXTCLK(uap)) 1307 uap->curregs[R1] |= EXT_INT_ENAB; 1308 write_zsreg(uap, R1, uap->curregs[R1]); 1309 } 1310 spin_unlock_irqrestore(&port->lock, flags); 1311} 1312 1313static const char *pmz_type(struct uart_port *port) 1314{ 1315 struct uart_pmac_port *uap = to_pmz(port); 1316 1317 if (ZS_IS_IRDA(uap)) 1318 return "Z85c30 ESCC - Infrared port"; 1319 else if (ZS_IS_INTMODEM(uap)) 1320 return "Z85c30 ESCC - Internal modem"; 1321 return "Z85c30 ESCC - Serial port"; 1322} 1323 1324/* We do not request/release mappings of the registers here, this 1325 * happens at early serial probe time. 1326 */ 1327static void pmz_release_port(struct uart_port *port) 1328{ 1329} 1330 1331static int pmz_request_port(struct uart_port *port) 1332{ 1333 return 0; 1334} 1335 1336/* These do not need to do anything interesting either. */ 1337static void pmz_config_port(struct uart_port *port, int flags) 1338{ 1339} 1340 1341/* We do not support letting the user mess with the divisor, IRQ, etc. */ 1342static int pmz_verify_port(struct uart_port *port, struct serial_struct *ser) 1343{ 1344 return -EINVAL; 1345} 1346 1347static struct uart_ops pmz_pops = { 1348 .tx_empty = pmz_tx_empty, 1349 .set_mctrl = pmz_set_mctrl, 1350 .get_mctrl = pmz_get_mctrl, 1351 .stop_tx = pmz_stop_tx, 1352 .start_tx = pmz_start_tx, 1353 .stop_rx = pmz_stop_rx, 1354 .enable_ms = pmz_enable_ms, 1355 .break_ctl = pmz_break_ctl, 1356 .startup = pmz_startup, 1357 .shutdown = pmz_shutdown, 1358 .set_termios = pmz_set_termios, 1359 .type = pmz_type, 1360 .release_port = pmz_release_port, 1361 .request_port = pmz_request_port, 1362 .config_port = pmz_config_port, 1363 .verify_port = pmz_verify_port, 1364}; 1365 1366/* 1367 * Setup one port structure after probing, HW is down at this point, 1368 * Unlike sunzilog, we don't need to pre-init the spinlock as we don't 1369 * register our console before uart_add_one_port() is called 1370 */ 1371static int __init pmz_init_port(struct uart_pmac_port *uap) 1372{ 1373 struct device_node *np = uap->node; 1374 const char *conn; 1375 const struct slot_names_prop { 1376 int count; 1377 char name[1]; 1378 } *slots; 1379 int len; 1380 struct resource r_ports, r_rxdma, r_txdma; 1381 1382 /* 1383 * Request & map chip registers 1384 */ 1385 if (of_address_to_resource(np, 0, &r_ports)) 1386 return -ENODEV; 1387 uap->port.mapbase = r_ports.start; 1388 uap->port.membase = ioremap(uap->port.mapbase, 0x1000); 1389 1390 uap->control_reg = uap->port.membase; 1391 uap->data_reg = uap->control_reg + 0x10; 1392 1393 /* 1394 * Request & map DBDMA registers 1395 */ 1396#ifdef HAS_DBDMA 1397 if (of_address_to_resource(np, 1, &r_txdma) == 0 && 1398 of_address_to_resource(np, 2, &r_rxdma) == 0) 1399 uap->flags |= PMACZILOG_FLAG_HAS_DMA; 1400#else 1401 memset(&r_txdma, 0, sizeof(struct resource)); 1402 memset(&r_rxdma, 0, sizeof(struct resource)); 1403#endif 1404 if (ZS_HAS_DMA(uap)) { 1405 uap->tx_dma_regs = ioremap(r_txdma.start, 0x100); 1406 if (uap->tx_dma_regs == NULL) { 1407 uap->flags &= ~PMACZILOG_FLAG_HAS_DMA; 1408 goto no_dma; 1409 } 1410 uap->rx_dma_regs = ioremap(r_rxdma.start, 0x100); 1411 if (uap->rx_dma_regs == NULL) { 1412 iounmap(uap->tx_dma_regs); 1413 uap->tx_dma_regs = NULL; 1414 uap->flags &= ~PMACZILOG_FLAG_HAS_DMA; 1415 goto no_dma; 1416 } 1417 uap->tx_dma_irq = irq_of_parse_and_map(np, 1); 1418 uap->rx_dma_irq = irq_of_parse_and_map(np, 2); 1419 } 1420no_dma: 1421 1422 /* 1423 * Detect port type 1424 */ 1425 if (of_device_is_compatible(np, "cobalt")) 1426 uap->flags |= PMACZILOG_FLAG_IS_INTMODEM; 1427 conn = of_get_property(np, "AAPL,connector", &len); 1428 if (conn && (strcmp(conn, "infrared") == 0)) 1429 uap->flags |= PMACZILOG_FLAG_IS_IRDA; 1430 uap->port_type = PMAC_SCC_ASYNC; 1431 /* 1999 Powerbook G3 has slot-names property instead */ 1432 slots = of_get_property(np, "slot-names", &len); 1433 if (slots && slots->count > 0) { 1434 if (strcmp(slots->name, "IrDA") == 0) 1435 uap->flags |= PMACZILOG_FLAG_IS_IRDA; 1436 else if (strcmp(slots->name, "Modem") == 0) 1437 uap->flags |= PMACZILOG_FLAG_IS_INTMODEM; 1438 } 1439 if (ZS_IS_IRDA(uap)) 1440 uap->port_type = PMAC_SCC_IRDA; 1441 if (ZS_IS_INTMODEM(uap)) { 1442 struct device_node* i2c_modem = 1443 of_find_node_by_name(NULL, "i2c-modem"); 1444 if (i2c_modem) { 1445 const char* mid = 1446 of_get_property(i2c_modem, "modem-id", NULL); 1447 if (mid) switch(*mid) { 1448 case 0x04 : 1449 case 0x05 : 1450 case 0x07 : 1451 case 0x08 : 1452 case 0x0b : 1453 case 0x0c : 1454 uap->port_type = PMAC_SCC_I2S1; 1455 } 1456 printk(KERN_INFO "pmac_zilog: i2c-modem detected, id: %d\n", 1457 mid ? (*mid) : 0); 1458 of_node_put(i2c_modem); 1459 } else { 1460 printk(KERN_INFO "pmac_zilog: serial modem detected\n"); 1461 } 1462 } 1463 1464 /* 1465 * Init remaining bits of "port" structure 1466 */ 1467 uap->port.iotype = UPIO_MEM; 1468 uap->port.irq = irq_of_parse_and_map(np, 0); 1469 uap->port.uartclk = ZS_CLOCK; 1470 uap->port.fifosize = 1; 1471 uap->port.ops = &pmz_pops; 1472 uap->port.type = PORT_PMAC_ZILOG; 1473 uap->port.flags = 0; 1474 1475 /* Setup some valid baud rate information in the register 1476 * shadows so we don't write crap there before baud rate is 1477 * first initialized. 1478 */ 1479 pmz_convert_to_zs(uap, CS8, 0, 9600); 1480 1481 return 0; 1482} 1483 1484/* 1485 * Get rid of a port on module removal 1486 */ 1487static void pmz_dispose_port(struct uart_pmac_port *uap) 1488{ 1489 struct device_node *np; 1490 1491 np = uap->node; 1492 iounmap(uap->rx_dma_regs); 1493 iounmap(uap->tx_dma_regs); 1494 iounmap(uap->control_reg); 1495 uap->node = NULL; 1496 of_node_put(np); 1497 memset(uap, 0, sizeof(struct uart_pmac_port)); 1498} 1499 1500/* 1501 * Called upon match with an escc node in the devive-tree. 1502 */ 1503static int pmz_attach(struct macio_dev *mdev, const struct of_device_id *match) 1504{ 1505 int i; 1506 1507 /* Iterate the pmz_ports array to find a matching entry 1508 */ 1509 for (i = 0; i < MAX_ZS_PORTS; i++) 1510 if (pmz_ports[i].node == mdev->ofdev.node) { 1511 struct uart_pmac_port *uap = &pmz_ports[i]; 1512 1513 uap->dev = mdev; 1514 dev_set_drvdata(&mdev->ofdev.dev, uap); 1515 if (macio_request_resources(uap->dev, "pmac_zilog")) 1516 printk(KERN_WARNING "%s: Failed to request resource" 1517 ", port still active\n", 1518 uap->node->name); 1519 else 1520 uap->flags |= PMACZILOG_FLAG_RSRC_REQUESTED; 1521 return 0; 1522 } 1523 return -ENODEV; 1524} 1525 1526/* 1527 * That one should not be called, macio isn't really a hotswap device, 1528 * we don't expect one of those serial ports to go away... 1529 */ 1530static int pmz_detach(struct macio_dev *mdev) 1531{ 1532 struct uart_pmac_port *uap = dev_get_drvdata(&mdev->ofdev.dev); 1533 1534 if (!uap) 1535 return -ENODEV; 1536 1537 if (uap->flags & PMACZILOG_FLAG_RSRC_REQUESTED) { 1538 macio_release_resources(uap->dev); 1539 uap->flags &= ~PMACZILOG_FLAG_RSRC_REQUESTED; 1540 } 1541 dev_set_drvdata(&mdev->ofdev.dev, NULL); 1542 uap->dev = NULL; 1543 1544 return 0; 1545} 1546 1547 1548static int pmz_suspend(struct macio_dev *mdev, pm_message_t pm_state) 1549{ 1550 struct uart_pmac_port *uap = dev_get_drvdata(&mdev->ofdev.dev); 1551 struct uart_state *state; 1552 unsigned long flags; 1553 1554 if (uap == NULL) { 1555 printk("HRM... pmz_suspend with NULL uap\n"); 1556 return 0; 1557 } 1558 1559 if (pm_state.event == mdev->ofdev.dev.power.power_state.event) 1560 return 0; 1561 1562 pmz_debug("suspend, switching to state %d\n", pm_state); 1563 1564 state = pmz_uart_reg.state + uap->port.line; 1565 1566 mutex_lock(&pmz_irq_mutex); 1567 mutex_lock(&state->mutex); 1568 1569 spin_lock_irqsave(&uap->port.lock, flags); 1570 1571 if (ZS_IS_OPEN(uap) || ZS_IS_CONS(uap)) { 1572 /* Disable receiver and transmitter. */ 1573 uap->curregs[R3] &= ~RxENABLE; 1574 uap->curregs[R5] &= ~TxENABLE; 1575 1576 /* Disable all interrupts and BRK assertion. */ 1577 uap->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK); 1578 uap->curregs[R5] &= ~SND_BRK; 1579 pmz_load_zsregs(uap, uap->curregs); 1580 uap->flags |= PMACZILOG_FLAG_IS_ASLEEP; 1581 mb(); 1582 } 1583 1584 spin_unlock_irqrestore(&uap->port.lock, flags); 1585 1586 if (ZS_IS_OPEN(uap) || ZS_IS_OPEN(uap->mate)) 1587 if (ZS_IS_ASLEEP(uap->mate) && ZS_IS_IRQ_ON(pmz_get_port_A(uap))) { 1588 pmz_get_port_A(uap)->flags &= ~PMACZILOG_FLAG_IS_IRQ_ON; 1589 disable_irq(uap->port.irq); 1590 } 1591 1592 if (ZS_IS_CONS(uap)) 1593 uap->port.cons->flags &= ~CON_ENABLED; 1594 1595 /* Shut the chip down */ 1596 pmz_set_scc_power(uap, 0); 1597 1598 mutex_unlock(&state->mutex); 1599 mutex_unlock(&pmz_irq_mutex); 1600 1601 pmz_debug("suspend, switching complete\n"); 1602 1603 mdev->ofdev.dev.power.power_state = pm_state; 1604 1605 return 0; 1606} 1607 1608 1609static int pmz_resume(struct macio_dev *mdev) 1610{ 1611 struct uart_pmac_port *uap = dev_get_drvdata(&mdev->ofdev.dev); 1612 struct uart_state *state; 1613 unsigned long flags; 1614 int pwr_delay = 0; 1615 1616 if (uap == NULL) 1617 return 0; 1618 1619 if (mdev->ofdev.dev.power.power_state.event == PM_EVENT_ON) 1620 return 0; 1621 1622 pmz_debug("resume, switching to state 0\n"); 1623 1624 state = pmz_uart_reg.state + uap->port.line; 1625 1626 mutex_lock(&pmz_irq_mutex); 1627 mutex_lock(&state->mutex); 1628 1629 spin_lock_irqsave(&uap->port.lock, flags); 1630 if (!ZS_IS_OPEN(uap) && !ZS_IS_CONS(uap)) { 1631 spin_unlock_irqrestore(&uap->port.lock, flags); 1632 goto bail; 1633 } 1634 pwr_delay = __pmz_startup(uap); 1635 1636 /* Take care of config that may have changed while asleep */ 1637 __pmz_set_termios(&uap->port, &uap->termios_cache, NULL); 1638 1639 if (ZS_IS_OPEN(uap)) { 1640 /* Enable interrupts */ 1641 uap->curregs[R1] |= INT_ALL_Rx | TxINT_ENAB; 1642 if (!ZS_IS_EXTCLK(uap)) 1643 uap->curregs[R1] |= EXT_INT_ENAB; 1644 write_zsreg(uap, R1, uap->curregs[R1]); 1645 } 1646 1647 spin_unlock_irqrestore(&uap->port.lock, flags); 1648 1649 if (ZS_IS_CONS(uap)) 1650 uap->port.cons->flags |= CON_ENABLED; 1651 1652 /* Re-enable IRQ on the controller */ 1653 if (ZS_IS_OPEN(uap) && !ZS_IS_IRQ_ON(pmz_get_port_A(uap))) { 1654 pmz_get_port_A(uap)->flags |= PMACZILOG_FLAG_IS_IRQ_ON; 1655 enable_irq(uap->port.irq); 1656 } 1657 1658 bail: 1659 mutex_unlock(&state->mutex); 1660 mutex_unlock(&pmz_irq_mutex); 1661 1662 /* Right now, we deal with delay by blocking here, I'll be 1663 * smarter later on 1664 */ 1665 if (pwr_delay != 0) { 1666 pmz_debug("pmz: delaying %d ms\n", pwr_delay); 1667 msleep(pwr_delay); 1668 } 1669 1670 pmz_debug("resume, switching complete\n"); 1671 1672 mdev->ofdev.dev.power.power_state.event = PM_EVENT_ON; 1673 1674 return 0; 1675} 1676 1677/* 1678 * Probe all ports in the system and build the ports array, we register 1679 * with the serial layer at this point, the macio-type probing is only 1680 * used later to "attach" to the sysfs tree so we get power management 1681 * events 1682 */ 1683static int __init pmz_probe(void) 1684{ 1685 struct device_node *node_p, *node_a, *node_b, *np; 1686 int count = 0; 1687 int rc; 1688 1689 /* 1690 * Find all escc chips in the system 1691 */ 1692 node_p = of_find_node_by_name(NULL, "escc"); 1693 while (node_p) { 1694 /* 1695 * First get channel A/B node pointers 1696 * 1697 * TODO: Add routines with proper locking to do that... 1698 */ 1699 node_a = node_b = NULL; 1700 for (np = NULL; (np = of_get_next_child(node_p, np)) != NULL;) { 1701 if (strncmp(np->name, "ch-a", 4) == 0) 1702 node_a = of_node_get(np); 1703 else if (strncmp(np->name, "ch-b", 4) == 0) 1704 node_b = of_node_get(np); 1705 } 1706 if (!node_a && !node_b) { 1707 of_node_put(node_a); 1708 of_node_put(node_b); 1709 printk(KERN_ERR "pmac_zilog: missing node %c for escc %s\n", 1710 (!node_a) ? 'a' : 'b', node_p->full_name); 1711 goto next; 1712 } 1713 1714 /* 1715 * Fill basic fields in the port structures 1716 */ 1717 pmz_ports[count].mate = &pmz_ports[count+1]; 1718 pmz_ports[count+1].mate = &pmz_ports[count]; 1719 pmz_ports[count].flags = PMACZILOG_FLAG_IS_CHANNEL_A; 1720 pmz_ports[count].node = node_a; 1721 pmz_ports[count+1].node = node_b; 1722 pmz_ports[count].port.line = count; 1723 pmz_ports[count+1].port.line = count+1; 1724 1725 /* 1726 * Setup the ports for real 1727 */ 1728 rc = pmz_init_port(&pmz_ports[count]); 1729 if (rc == 0 && node_b != NULL) 1730 rc = pmz_init_port(&pmz_ports[count+1]); 1731 if (rc != 0) { 1732 of_node_put(node_a); 1733 of_node_put(node_b); 1734 memset(&pmz_ports[count], 0, sizeof(struct uart_pmac_port)); 1735 memset(&pmz_ports[count+1], 0, sizeof(struct uart_pmac_port)); 1736 goto next; 1737 } 1738 count += 2; 1739next: 1740 node_p = of_find_node_by_name(node_p, "escc"); 1741 } 1742 pmz_ports_count = count; 1743 1744 return 0; 1745} 1746 1747#ifdef CONFIG_SERIAL_PMACZILOG_CONSOLE 1748 1749static void pmz_console_write(struct console *con, const char *s, unsigned int count); 1750static int __init pmz_console_setup(struct console *co, char *options); 1751 1752static struct console pmz_console = { 1753 .name = "ttyS", 1754 .write = pmz_console_write, 1755 .device = uart_console_device, 1756 .setup = pmz_console_setup, 1757 .flags = CON_PRINTBUFFER, 1758 .index = -1, 1759 .data = &pmz_uart_reg, 1760}; 1761 1762#define PMACZILOG_CONSOLE &pmz_console 1763#else /* CONFIG_SERIAL_PMACZILOG_CONSOLE */ 1764#define PMACZILOG_CONSOLE (NULL) 1765#endif /* CONFIG_SERIAL_PMACZILOG_CONSOLE */ 1766 1767/* 1768 * Register the driver, console driver and ports with the serial 1769 * core 1770 */ 1771static int __init pmz_register(void) 1772{ 1773 int i, rc; 1774 1775 pmz_uart_reg.nr = pmz_ports_count; 1776 pmz_uart_reg.cons = PMACZILOG_CONSOLE; 1777 pmz_uart_reg.minor = 64; 1778 1779 /* 1780 * Register this driver with the serial core 1781 */ 1782 rc = uart_register_driver(&pmz_uart_reg); 1783 if (rc) 1784 return rc; 1785 1786 /* 1787 * Register each port with the serial core 1788 */ 1789 for (i = 0; i < pmz_ports_count; i++) { 1790 struct uart_pmac_port *uport = &pmz_ports[i]; 1791 /* NULL node may happen on wallstreet */ 1792 if (uport->node != NULL) 1793 rc = uart_add_one_port(&pmz_uart_reg, &uport->port); 1794 if (rc) 1795 goto err_out; 1796 } 1797 1798 return 0; 1799err_out: 1800 while (i-- > 0) { 1801 struct uart_pmac_port *uport = &pmz_ports[i]; 1802 uart_remove_one_port(&pmz_uart_reg, &uport->port); 1803 } 1804 uart_unregister_driver(&pmz_uart_reg); 1805 return rc; 1806} 1807 1808static struct of_device_id pmz_match[] = 1809{ 1810 { 1811 .name = "ch-a", 1812 }, 1813 { 1814 .name = "ch-b", 1815 }, 1816 {}, 1817}; 1818MODULE_DEVICE_TABLE (of, pmz_match); 1819 1820static struct macio_driver pmz_driver = 1821{ 1822 .name = "pmac_zilog", 1823 .match_table = pmz_match, 1824 .probe = pmz_attach, 1825 .remove = pmz_detach, 1826 .suspend = pmz_suspend, 1827 .resume = pmz_resume, 1828}; 1829 1830static int __init init_pmz(void) 1831{ 1832 int rc, i; 1833 printk(KERN_INFO "%s\n", version); 1834 1835 /* 1836 * First, we need to do a direct OF-based probe pass. We 1837 * do that because we want serial console up before the 1838 * macio stuffs calls us back, and since that makes it 1839 * easier to pass the proper number of channels to 1840 * uart_register_driver() 1841 */ 1842 if (pmz_ports_count == 0) 1843 pmz_probe(); 1844 1845 /* 1846 * Bail early if no port found 1847 */ 1848 if (pmz_ports_count == 0) 1849 return -ENODEV; 1850 1851 /* 1852 * Now we register with the serial layer 1853 */ 1854 rc = pmz_register(); 1855 if (rc) { 1856 printk(KERN_ERR 1857 "pmac_zilog: Error registering serial device, disabling pmac_zilog.\n" 1858 "pmac_zilog: Did another serial driver already claim the minors?\n"); 1859 /* effectively "pmz_unprobe()" */ 1860 for (i=0; i < pmz_ports_count; i++) 1861 pmz_dispose_port(&pmz_ports[i]); 1862 return rc; 1863 } 1864 1865 /* 1866 * Then we register the macio driver itself 1867 */ 1868 return macio_register_driver(&pmz_driver); 1869} 1870 1871static void __exit exit_pmz(void) 1872{ 1873 int i; 1874 1875 /* Get rid of macio-driver (detach from macio) */ 1876 macio_unregister_driver(&pmz_driver); 1877 1878 for (i = 0; i < pmz_ports_count; i++) { 1879 struct uart_pmac_port *uport = &pmz_ports[i]; 1880 if (uport->node != NULL) { 1881 uart_remove_one_port(&pmz_uart_reg, &uport->port); 1882 pmz_dispose_port(uport); 1883 } 1884 } 1885 /* Unregister UART driver */ 1886 uart_unregister_driver(&pmz_uart_reg); 1887} 1888 1889#ifdef CONFIG_SERIAL_PMACZILOG_CONSOLE 1890 1891static void pmz_console_putchar(struct uart_port *port, int ch) 1892{ 1893 struct uart_pmac_port *uap = (struct uart_pmac_port *)port; 1894 1895 /* Wait for the transmit buffer to empty. */ 1896 while ((read_zsreg(uap, R0) & Tx_BUF_EMP) == 0) 1897 udelay(5); 1898 write_zsdata(uap, ch); 1899} 1900 1901/* 1902 * Print a string to the serial port trying not to disturb 1903 * any possible real use of the port... 1904 */ 1905static void pmz_console_write(struct console *con, const char *s, unsigned int count) 1906{ 1907 struct uart_pmac_port *uap = &pmz_ports[con->index]; 1908 unsigned long flags; 1909 1910 if (ZS_IS_ASLEEP(uap)) 1911 return; 1912 spin_lock_irqsave(&uap->port.lock, flags); 1913 1914 /* Turn of interrupts and enable the transmitter. */ 1915 write_zsreg(uap, R1, uap->curregs[1] & ~TxINT_ENAB); 1916 write_zsreg(uap, R5, uap->curregs[5] | TxENABLE | RTS | DTR); 1917 1918 uart_console_write(&uap->port, s, count, pmz_console_putchar); 1919 1920 /* Restore the values in the registers. */ 1921 write_zsreg(uap, R1, uap->curregs[1]); 1922 /* Don't disable the transmitter. */ 1923 1924 spin_unlock_irqrestore(&uap->port.lock, flags); 1925} 1926 1927/* 1928 * Setup the serial console 1929 */ 1930static int __init pmz_console_setup(struct console *co, char *options) 1931{ 1932 struct uart_pmac_port *uap; 1933 struct uart_port *port; 1934 int baud = 38400; 1935 int bits = 8; 1936 int parity = 'n'; 1937 int flow = 'n'; 1938 unsigned long pwr_delay; 1939 1940 /* 1941 * XServe's default to 57600 bps 1942 */ 1943 if (machine_is_compatible("RackMac1,1") 1944 || machine_is_compatible("RackMac1,2") 1945 || machine_is_compatible("MacRISC4")) 1946 baud = 57600; 1947 1948 /* 1949 * Check whether an invalid uart number has been specified, and 1950 * if so, search for the first available port that does have 1951 * console support. 1952 */ 1953 if (co->index >= pmz_ports_count) 1954 co->index = 0; 1955 uap = &pmz_ports[co->index]; 1956 if (uap->node == NULL) 1957 return -ENODEV; 1958 port = &uap->port; 1959 1960 /* 1961 * Mark port as beeing a console 1962 */ 1963 uap->flags |= PMACZILOG_FLAG_IS_CONS; 1964 1965 /* 1966 * Temporary fix for uart layer who didn't setup the spinlock yet 1967 */ 1968 spin_lock_init(&port->lock); 1969 1970 /* 1971 * Enable the hardware 1972 */ 1973 pwr_delay = __pmz_startup(uap); 1974 if (pwr_delay) 1975 mdelay(pwr_delay); 1976 1977 if (options) 1978 uart_parse_options(options, &baud, &parity, &bits, &flow); 1979 1980 return uart_set_options(port, co, baud, parity, bits, flow); 1981} 1982 1983static int __init pmz_console_init(void) 1984{ 1985 /* Probe ports */ 1986 pmz_probe(); 1987 1988 /* TODO: Autoprobe console based on OF */ 1989 /* pmz_console.index = i; */ 1990 register_console(&pmz_console); 1991 1992 return 0; 1993 1994} 1995console_initcall(pmz_console_init); 1996#endif /* CONFIG_SERIAL_PMACZILOG_CONSOLE */ 1997 1998module_init(init_pmz); 1999module_exit(exit_pmz); 2000