Lines Matching refs:control_reg
141 static u32 set_spdif_bits(struct echoaudio *chip, u32 control_reg, u32 rate)
143 control_reg &= E3G_SPDIF_FORMAT_CLEAR_MASK;
147 control_reg |= E3G_SPDIF_SAMPLE_RATE0 | E3G_SPDIF_SAMPLE_RATE1;
151 control_reg |= E3G_SPDIF_SAMPLE_RATE0;
154 control_reg |= E3G_SPDIF_SAMPLE_RATE1;
159 control_reg |= E3G_SPDIF_PRO_MODE;
162 control_reg |= E3G_SPDIF_NOT_AUDIO;
164 control_reg |= E3G_SPDIF_24_BIT | E3G_SPDIF_TWO_CHANNEL |
167 return control_reg;
175 u32 control_reg;
177 control_reg = le32_to_cpu(chip->comm_page->control_register);
179 control_reg = set_spdif_bits(chip, control_reg, chip->sample_rate);
180 return write_control_reg(chip, control_reg, get_frq_reg(chip), 0);
257 u32 control_reg, clock, base_rate, frq_reg;
274 control_reg = le32_to_cpu(chip->comm_page->control_register);
275 control_reg &= E3G_CLOCK_CLEAR_MASK;
300 control_reg |= clock;
301 control_reg = set_spdif_bits(chip, control_reg, rate);
315 DE_ACT(("SetSampleRate: %d clock %x\n", rate, control_reg));
318 return write_control_reg(chip, control_reg, frq_reg, 0);
326 u32 control_reg, clocks_from_dsp;
331 control_reg = le32_to_cpu(chip->comm_page->control_register) &
344 control_reg |= E3G_SPDIF_CLOCK;
346 control_reg |= E3G_DOUBLE_SPEED_MODE;
348 control_reg &= ~E3G_DOUBLE_SPEED_MODE;
354 control_reg |= E3G_ADAT_CLOCK;
355 control_reg &= ~E3G_DOUBLE_SPEED_MODE;
359 control_reg |= E3G_WORD_CLOCK;
361 control_reg |= E3G_DOUBLE_SPEED_MODE;
363 control_reg &= ~E3G_DOUBLE_SPEED_MODE;
371 return write_control_reg(chip, control_reg, get_frq_reg(chip), 1);
378 u32 control_reg;
406 control_reg = le32_to_cpu(chip->comm_page->control_register);
407 control_reg &= E3G_DIGITAL_MODE_CLEAR_MASK;
412 control_reg |= E3G_SPDIF_OPTICAL_MODE;
418 control_reg |= E3G_ADAT_MODE;
419 control_reg &= ~E3G_DOUBLE_SPEED_MODE; /* @@ useless */
423 err = write_control_reg(chip, control_reg, get_frq_reg(chip), 1);