Lines Matching refs:control_reg
119 u32 control_reg;
152 control_reg = GML_CONVERTER_ENABLE | GML_48KHZ;
153 err = write_control_reg(chip, control_reg, TRUE);
200 u32 control_reg, clock;
246 control_reg = le32_to_cpu(chip->comm_page->control_register);
247 control_reg &= GML_CLOCK_CLEAR_MASK;
248 control_reg &= GML_SPDIF_RATE_CLEAR_MASK;
263 if (control_reg & GML_SPDIF_PRO_MODE)
287 control_reg |= clock;
293 return write_control_reg(chip, control_reg, force_write);
300 u32 control_reg, clocks_from_dsp;
310 control_reg = le32_to_cpu(chip->comm_page->control_register) &
329 control_reg |= GML_SPDIF_CLOCK;
331 control_reg |= GML_DOUBLE_SPEED_MODE;
333 control_reg &= ~GML_DOUBLE_SPEED_MODE;
343 control_reg |= GML_WORD_CLOCK;
345 control_reg |= GML_DOUBLE_SPEED_MODE;
347 control_reg &= ~GML_DOUBLE_SPEED_MODE;
353 control_reg |= GML_ADAT_CLOCK;
354 control_reg &= ~GML_DOUBLE_SPEED_MODE;
362 return write_control_reg(chip, control_reg, TRUE);
369 u32 control_reg;
397 control_reg = le32_to_cpu(chip->comm_page->control_register);
398 control_reg &= GML_DIGITAL_MODE_CLEAR_MASK;
403 control_reg |= GML_SPDIF_OPTICAL_MODE;
415 control_reg |= GML_ADAT_MODE;
416 control_reg &= ~GML_DOUBLE_SPEED_MODE;
420 err = write_control_reg(chip, control_reg, FALSE);