/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/drivers/char/drm/ |
H A D | mga_state.c | 47 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; local 48 drm_mga_context_regs_t *ctx = &sarea_priv->context_state; 71 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; local 72 drm_mga_context_regs_t *ctx = &sarea_priv->context_state; 94 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; local 95 drm_mga_context_regs_t *ctx = &sarea_priv->context_state; 121 drm_mga_sarea_t *sarea_priv local 149 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; local 189 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; local 228 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; local 255 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; local 332 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; local 353 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; local 386 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; local 405 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; local 422 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; local 486 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; local 574 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; local 629 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; local 677 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; local 772 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; local 835 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; local 861 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; local 1000 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; local [all...] |
H A D | via_video.c | 40 XVMCLOCKPTR(dev_priv->sarea_priv, i)->lock = 0; 53 if (!dev_priv->sarea_priv) 57 lock = (volatile int *)XVMCLOCKPTR(dev_priv->sarea_priv, i); 74 drm_via_sarea_t *sAPriv = dev_priv->sarea_priv;
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H A D | r128_state.c | 85 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; local 86 drm_r128_context_regs_t *ctx = &sarea_priv->context_state; 100 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; local 101 drm_r128_context_regs_t *ctx = &sarea_priv->context_state; 126 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; local 127 drm_r128_context_regs_t *ctx = &sarea_priv->context_state; 142 drm_r128_sarea_t *sarea_priv local 161 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; local 176 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; local 203 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; local 226 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; local 359 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; local 464 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; local 574 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; local 699 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; local 1239 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; local 1326 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; local [all...] |
H A D | i830_dma.c | 277 dev_priv->sarea_priv->perf_boxes |= I830_BOX_WAIT; 296 dev_priv->sarea_priv->perf_boxes |= I830_BOX_RING_EMPTY; 373 dev_priv->sarea_priv = (drm_i830_sarea_t *) 699 drm_i830_sarea_t *sarea_priv = dev_priv->sarea_priv; local 700 unsigned int dirty = sarea_priv->dirty; 705 i830EmitDestVerified(dev, sarea_priv->BufferState); 706 sarea_priv->dirty &= ~I830_UPLOAD_BUFFERS; 710 i830EmitContextVerified(dev, sarea_priv->ContextState); 711 sarea_priv 878 drm_i830_sarea_t *sarea_priv = dev_priv->sarea_priv; local 970 drm_i830_sarea_t *sarea_priv = dev_priv->sarea_priv; local 1085 drm_i830_sarea_t *sarea_priv = dev_priv->sarea_priv; local 1292 drm_i830_sarea_t *sarea_priv = (drm_i830_sarea_t *) local 1405 drm_i830_sarea_t *sarea_priv = (drm_i830_sarea_t *) local 1421 drm_i830_sarea_t *sarea_priv = (drm_i830_sarea_t *) local [all...] |
H A D | i810_dma.c | 365 dev_priv->sarea_priv = (drm_i810_sarea_t *) 643 drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv; local 644 unsigned int dirty = sarea_priv->dirty; 649 i810EmitDestVerified(dev, sarea_priv->BufferState); 650 sarea_priv->dirty &= ~I810_UPLOAD_BUFFERS; 654 i810EmitContextVerified(dev, sarea_priv->ContextState); 655 sarea_priv->dirty &= ~I810_UPLOAD_CTX; 659 i810EmitTexVerified(dev, sarea_priv->TexState[0]); 660 sarea_priv 676 drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv; local 749 drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv; local 797 drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv; local 1023 drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *) local 1095 drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *) local 1111 drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *) local 1152 drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv; local 1215 drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *) local [all...] |
H A D | i915_irq.c | 54 drm_i915_sarea_t *sarea_priv = dev_priv->sarea_priv; local 60 u32 pitchropcpp = (sarea_priv->pitch * cpp) | (0xcc << 16) | 133 OUT_RING(sarea_priv->width | sarea_priv->height << 16); 134 OUT_RING(sarea_priv->width | sarea_priv->height << 16); 139 sarea_priv->ctxOwner = DRM_KERNEL_CONTEXT; 142 slice[0] = max(sarea_priv->pipeA_h / nhits, 1); 143 slice[1] = max(sarea_priv [all...] |
H A D | radeon_state.c | 746 x += dev_priv->sarea_priv->boxes[0].x1; 747 y += dev_priv->sarea_priv->boxes[0].y1; 775 if (dev_priv->sarea_priv->pfCurrentPage == 1) { 851 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; local 853 int nbox = sarea_priv->nbox; 854 drm_clip_rect_t *pbox = sarea_priv->boxes; 863 if (dev_priv->sarea_priv->pfCurrentPage == 1) { 889 dev_priv->sarea_priv->ctx_owner = 0; 966 dev_priv->sarea_priv 1326 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; local 1484 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; local 1581 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; local 2095 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; local 2173 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; local 2195 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; local 2278 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; local 2496 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; local [all...] |
H A D | i915_dma.c | 65 dev_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT; 88 dev_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY; 151 dev_priv->sarea_priv = (drm_i915_sarea_t *) 181 dev_priv->sarea_priv->pf_current_page = dev_priv->current_page; 444 dev_priv->sarea_priv->last_enqueue = ++dev_priv->counter; 447 dev_priv->sarea_priv->last_enqueue = dev_priv->counter = 1; 543 dev_priv->sarea_priv->pf_current_page); 570 dev_priv->sarea_priv->last_enqueue = dev_priv->counter++; 579 dev_priv->sarea_priv->pf_current_page = dev_priv->current_page; 605 drm_i915_sarea_t *sarea_priv local 639 drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *) local [all...] |
H A D | mga_dma.c | 79 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; local 90 sarea_priv->last_wrap = 0; 201 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; local 205 sarea_priv->last_wrap++; 206 DRM_DEBUG(" wrap = %d\n", sarea_priv->last_wrap); 230 dev_priv->sarea_priv->last_dispatch, 318 wrap = dev_priv->sarea_priv->last_wrap; 848 dev_priv->sarea_priv [all...] |
H A D | i915_mem.c | 49 drm_i915_sarea_t *sarea_priv = dev_priv->sarea_priv; local 63 age = ++sarea_priv->texAge; 64 list = sarea_priv->texList;
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H A D | via_map.c | 57 dev_priv->sarea_priv =
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H A D | r128_drv.h | 80 drm_r128_sarea_t *sarea_priv; member in struct:drm_r128_private 439 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; \ 440 if ( sarea_priv->last_dispatch >= R128_MAX_VB_AGE ) { \ 443 sarea_priv->last_dispatch = 0; \
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H A D | via_drv.h | 61 drm_via_sarea_t *sarea_priv; member in struct:drm_via_private
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H A D | r128_cce.c | 509 dev_priv->sarea_priv = 553 dev_priv->sarea_priv->last_frame = 0; 554 R128_WRITE(R128_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame); 556 dev_priv->sarea_priv->last_dispatch = 0; 557 R128_WRITE(R128_LAST_DISPATCH_REG, dev_priv->sarea_priv->last_dispatch);
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H A D | i830_irq.c | 85 dev_priv->sarea_priv->perf_boxes |= I830_BOX_WAIT;
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H A D | radeon_drv.h | 210 drm_radeon_sarea_t *sarea_priv; member in struct:drm_radeon_private 1070 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; \ 1071 if ( sarea_priv->last_dispatch >= RADEON_MAX_VB_AGE ) { \ 1074 sarea_priv->last_dispatch = 0; \
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H A D | i810_drv.h | 83 drm_i810_sarea_t *sarea_priv; member in struct:drm_i810_private
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H A D | i830_drv.h | 89 drm_i830_sarea_t *sarea_priv; member in struct:drm_i830_private
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H A D | i915_drv.h | 87 drm_i915_sarea_t *sarea_priv; member in struct:drm_i915_private
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H A D | radeon_cp.c | 1215 dev_priv->sarea_priv->last_frame = dev_priv->scratch[0] = 0; 1216 RADEON_WRITE(RADEON_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame); 1218 dev_priv->sarea_priv->last_dispatch = dev_priv->scratch[1] = 0; 1220 dev_priv->sarea_priv->last_dispatch); 1222 dev_priv->sarea_priv->last_clear = dev_priv->scratch[2] = 0; 1223 RADEON_WRITE(RADEON_LAST_CLEAR_REG, dev_priv->sarea_priv->last_clear); 1541 dev_priv->sarea_priv =
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H A D | mga_drv.h | 79 drm_mga_sarea_t *sarea_priv; member in struct:drm_mga_private 368 entry->age.wrap = dev_priv->sarea_priv->last_wrap; \
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H A D | r300_cmdbuf.c | 711 buf_priv->age = ++dev_priv->sarea_priv->last_dispatch; 945 RADEON_DISPATCH_AGE(dev_priv->sarea_priv->last_dispatch);
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H A D | savage_drv.h | 128 drm_savage_sarea_t *sarea_priv; member in struct:drm_savage_private
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H A D | savage_bci.c | 818 dev_priv->sarea_priv =
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