Lines Matching refs:sarea_priv
365 dev_priv->sarea_priv = (drm_i810_sarea_t *)
643 drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv;
644 unsigned int dirty = sarea_priv->dirty;
649 i810EmitDestVerified(dev, sarea_priv->BufferState);
650 sarea_priv->dirty &= ~I810_UPLOAD_BUFFERS;
654 i810EmitContextVerified(dev, sarea_priv->ContextState);
655 sarea_priv->dirty &= ~I810_UPLOAD_CTX;
659 i810EmitTexVerified(dev, sarea_priv->TexState[0]);
660 sarea_priv->dirty &= ~I810_UPLOAD_TEX0;
664 i810EmitTexVerified(dev, sarea_priv->TexState[1]);
665 sarea_priv->dirty &= ~I810_UPLOAD_TEX1;
676 drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv;
677 int nbox = sarea_priv->nbox;
678 drm_clip_rect_t *pbox = sarea_priv->boxes;
749 drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv;
750 int nbox = sarea_priv->nbox;
751 drm_clip_rect_t *pbox = sarea_priv->boxes;
797 drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv;
798 drm_clip_rect_t *box = sarea_priv->boxes;
799 int nbox = sarea_priv->nbox;
813 if (sarea_priv->dirty)
817 unsigned int prim = (sarea_priv->vertex_prim & PR_MASK);
881 dev_priv->sarea_priv->pf_current_page);
915 dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;
1023 drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *)
1024 dev_priv->sarea_priv;
1045 sarea_priv->last_enqueue = dev_priv->counter - 1;
1046 sarea_priv->last_dispatch = (int)hw_status[5];
1095 drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *)
1096 dev_priv->sarea_priv;
1098 sarea_priv->last_dispatch = (int)hw_status[5];
1111 drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *)
1112 dev_priv->sarea_priv;
1128 sarea_priv->last_dispatch = (int)hw_status[5];
1152 drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv;
1168 sarea_priv->dirty = 0x7f;
1215 drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *)
1216 dev_priv->sarea_priv;
1232 sarea_priv->last_enqueue = dev_priv->counter - 1;
1233 sarea_priv->last_dispatch = (int)hw_status[5];
1300 dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;