1/* mga_dma.c -- DMA support for mga g200/g400 -*- linux-c -*- 2 * Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com 3 * 4 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. 5 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 6 * All Rights Reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice (including the next 16 * paragraph) shall be included in all copies or substantial portions of the 17 * Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 22 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 25 * DEALINGS IN THE SOFTWARE. 26 */ 27 28/** 29 * \file mga_dma.c 30 * DMA support for MGA G200 / G400. 31 * 32 * \author Rickard E. (Rik) Faith <faith@valinux.com> 33 * \author Jeff Hartmann <jhartmann@valinux.com> 34 * \author Keith Whitwell <keith@tungstengraphics.com> 35 * \author Gareth Hughes <gareth@valinux.com> 36 */ 37 38#include "drmP.h" 39#include "drm.h" 40#include "drm_sarea.h" 41#include "mga_drm.h" 42#include "mga_drv.h" 43 44#define MGA_DEFAULT_USEC_TIMEOUT 10000 45#define MGA_FREELIST_DEBUG 0 46 47#define MINIMAL_CLEANUP 0 48#define FULL_CLEANUP 1 49static int mga_do_cleanup_dma(drm_device_t *dev, int full_cleanup); 50 51/* ================================================================ 52 * Engine control 53 */ 54 55int mga_do_wait_for_idle(drm_mga_private_t * dev_priv) 56{ 57 u32 status = 0; 58 int i; 59 DRM_DEBUG("\n"); 60 61 for (i = 0; i < dev_priv->usec_timeout; i++) { 62 status = MGA_READ(MGA_STATUS) & MGA_ENGINE_IDLE_MASK; 63 if (status == MGA_ENDPRDMASTS) { 64 MGA_WRITE8(MGA_CRTC_INDEX, 0); 65 return 0; 66 } 67 DRM_UDELAY(1); 68 } 69 70#if MGA_DMA_DEBUG 71 DRM_ERROR("failed!\n"); 72 DRM_INFO(" status=0x%08x\n", status); 73#endif 74 return DRM_ERR(EBUSY); 75} 76 77static int mga_do_dma_reset(drm_mga_private_t * dev_priv) 78{ 79 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; 80 drm_mga_primary_buffer_t *primary = &dev_priv->prim; 81 82 DRM_DEBUG("\n"); 83 84 /* The primary DMA stream should look like new right about now. 85 */ 86 primary->tail = 0; 87 primary->space = primary->size; 88 primary->last_flush = 0; 89 90 sarea_priv->last_wrap = 0; 91 92 93 94 return 0; 95} 96 97/* ================================================================ 98 * Primary DMA stream 99 */ 100 101void mga_do_dma_flush(drm_mga_private_t * dev_priv) 102{ 103 drm_mga_primary_buffer_t *primary = &dev_priv->prim; 104 u32 head, tail; 105 u32 status = 0; 106 int i; 107 DMA_LOCALS; 108 DRM_DEBUG("\n"); 109 110 /* We need to wait so that we can do an safe flush */ 111 for (i = 0; i < dev_priv->usec_timeout; i++) { 112 status = MGA_READ(MGA_STATUS) & MGA_ENGINE_IDLE_MASK; 113 if (status == MGA_ENDPRDMASTS) 114 break; 115 DRM_UDELAY(1); 116 } 117 118 if (primary->tail == primary->last_flush) { 119 DRM_DEBUG(" bailing out...\n"); 120 return; 121 } 122 123 tail = primary->tail + dev_priv->primary->offset; 124 125 /* We need to pad the stream between flushes, as the card 126 * actually (partially?) reads the first of these commands. 127 * See page 4-16 in the G400 manual, middle of the page or so. 128 */ 129 BEGIN_DMA(1); 130 131 DMA_BLOCK(MGA_DMAPAD, 0x00000000, 132 MGA_DMAPAD, 0x00000000, 133 MGA_DMAPAD, 0x00000000, MGA_DMAPAD, 0x00000000); 134 135 ADVANCE_DMA(); 136 137 primary->last_flush = primary->tail; 138 139 head = MGA_READ(MGA_PRIMADDRESS); 140 141 if (head <= tail) { 142 primary->space = primary->size - primary->tail; 143 } else { 144 primary->space = head - tail; 145 } 146 147 DRM_DEBUG(" head = 0x%06lx\n", head - dev_priv->primary->offset); 148 DRM_DEBUG(" tail = 0x%06lx\n", tail - dev_priv->primary->offset); 149 DRM_DEBUG(" space = 0x%06x\n", primary->space); 150 151 mga_flush_write_combine(); 152 MGA_WRITE(MGA_PRIMEND, tail | dev_priv->dma_access); 153 154 DRM_DEBUG("done.\n"); 155} 156 157void mga_do_dma_wrap_start(drm_mga_private_t * dev_priv) 158{ 159 drm_mga_primary_buffer_t *primary = &dev_priv->prim; 160 u32 head, tail; 161 DMA_LOCALS; 162 DRM_DEBUG("\n"); 163 164 BEGIN_DMA_WRAP(); 165 166 DMA_BLOCK(MGA_DMAPAD, 0x00000000, 167 MGA_DMAPAD, 0x00000000, 168 MGA_DMAPAD, 0x00000000, MGA_DMAPAD, 0x00000000); 169 170 ADVANCE_DMA(); 171 172 tail = primary->tail + dev_priv->primary->offset; 173 174 primary->tail = 0; 175 primary->last_flush = 0; 176 primary->last_wrap++; 177 178 head = MGA_READ(MGA_PRIMADDRESS); 179 180 if (head == dev_priv->primary->offset) { 181 primary->space = primary->size; 182 } else { 183 primary->space = head - dev_priv->primary->offset; 184 } 185 186 DRM_DEBUG(" head = 0x%06lx\n", head - dev_priv->primary->offset); 187 DRM_DEBUG(" tail = 0x%06x\n", primary->tail); 188 DRM_DEBUG(" wrap = %d\n", primary->last_wrap); 189 DRM_DEBUG(" space = 0x%06x\n", primary->space); 190 191 mga_flush_write_combine(); 192 MGA_WRITE(MGA_PRIMEND, tail | dev_priv->dma_access); 193 194 set_bit(0, &primary->wrapped); 195 DRM_DEBUG("done.\n"); 196} 197 198void mga_do_dma_wrap_end(drm_mga_private_t * dev_priv) 199{ 200 drm_mga_primary_buffer_t *primary = &dev_priv->prim; 201 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; 202 u32 head = dev_priv->primary->offset; 203 DRM_DEBUG("\n"); 204 205 sarea_priv->last_wrap++; 206 DRM_DEBUG(" wrap = %d\n", sarea_priv->last_wrap); 207 208 mga_flush_write_combine(); 209 MGA_WRITE(MGA_PRIMADDRESS, head | MGA_DMA_GENERAL); 210 211 clear_bit(0, &primary->wrapped); 212 DRM_DEBUG("done.\n"); 213} 214 215/* ================================================================ 216 * Freelist management 217 */ 218 219#define MGA_BUFFER_USED ~0 220#define MGA_BUFFER_FREE 0 221 222#if MGA_FREELIST_DEBUG 223static void mga_freelist_print(drm_device_t * dev) 224{ 225 drm_mga_private_t *dev_priv = dev->dev_private; 226 drm_mga_freelist_t *entry; 227 228 DRM_INFO("\n"); 229 DRM_INFO("current dispatch: last=0x%x done=0x%x\n", 230 dev_priv->sarea_priv->last_dispatch, 231 (unsigned int)(MGA_READ(MGA_PRIMADDRESS) - 232 dev_priv->primary->offset)); 233 DRM_INFO("current freelist:\n"); 234 235 for (entry = dev_priv->head->next; entry; entry = entry->next) { 236 DRM_INFO(" %p idx=%2d age=0x%x 0x%06lx\n", 237 entry, entry->buf->idx, entry->age.head, 238 entry->age.head - dev_priv->primary->offset); 239 } 240 DRM_INFO("\n"); 241} 242#endif 243 244static int mga_freelist_init(drm_device_t * dev, drm_mga_private_t * dev_priv) 245{ 246 drm_device_dma_t *dma = dev->dma; 247 drm_buf_t *buf; 248 drm_mga_buf_priv_t *buf_priv; 249 drm_mga_freelist_t *entry; 250 int i; 251 DRM_DEBUG("count=%d\n", dma->buf_count); 252 253 dev_priv->head = drm_alloc(sizeof(drm_mga_freelist_t), DRM_MEM_DRIVER); 254 if (dev_priv->head == NULL) 255 return DRM_ERR(ENOMEM); 256 257 memset(dev_priv->head, 0, sizeof(drm_mga_freelist_t)); 258 SET_AGE(&dev_priv->head->age, MGA_BUFFER_USED, 0); 259 260 for (i = 0; i < dma->buf_count; i++) { 261 buf = dma->buflist[i]; 262 buf_priv = buf->dev_private; 263 264 entry = drm_alloc(sizeof(drm_mga_freelist_t), DRM_MEM_DRIVER); 265 if (entry == NULL) 266 return DRM_ERR(ENOMEM); 267 268 memset(entry, 0, sizeof(drm_mga_freelist_t)); 269 270 entry->next = dev_priv->head->next; 271 entry->prev = dev_priv->head; 272 SET_AGE(&entry->age, MGA_BUFFER_FREE, 0); 273 entry->buf = buf; 274 275 if (dev_priv->head->next != NULL) 276 dev_priv->head->next->prev = entry; 277 if (entry->next == NULL) 278 dev_priv->tail = entry; 279 280 buf_priv->list_entry = entry; 281 buf_priv->discard = 0; 282 buf_priv->dispatched = 0; 283 284 dev_priv->head->next = entry; 285 } 286 287 return 0; 288} 289 290static void mga_freelist_cleanup(drm_device_t * dev) 291{ 292 drm_mga_private_t *dev_priv = dev->dev_private; 293 drm_mga_freelist_t *entry; 294 drm_mga_freelist_t *next; 295 DRM_DEBUG("\n"); 296 297 entry = dev_priv->head; 298 while (entry) { 299 next = entry->next; 300 drm_free(entry, sizeof(drm_mga_freelist_t), DRM_MEM_DRIVER); 301 entry = next; 302 } 303 304 dev_priv->head = dev_priv->tail = NULL; 305} 306 307 308static drm_buf_t *mga_freelist_get(drm_device_t * dev) 309{ 310 drm_mga_private_t *dev_priv = dev->dev_private; 311 drm_mga_freelist_t *next; 312 drm_mga_freelist_t *prev; 313 drm_mga_freelist_t *tail = dev_priv->tail; 314 u32 head, wrap; 315 DRM_DEBUG("\n"); 316 317 head = MGA_READ(MGA_PRIMADDRESS); 318 wrap = dev_priv->sarea_priv->last_wrap; 319 320 DRM_DEBUG(" tail=0x%06lx %d\n", 321 tail->age.head ? 322 tail->age.head - dev_priv->primary->offset : 0, 323 tail->age.wrap); 324 DRM_DEBUG(" head=0x%06lx %d\n", 325 head - dev_priv->primary->offset, wrap); 326 327 if (TEST_AGE(&tail->age, head, wrap)) { 328 prev = dev_priv->tail->prev; 329 next = dev_priv->tail; 330 prev->next = NULL; 331 next->prev = next->next = NULL; 332 dev_priv->tail = prev; 333 SET_AGE(&next->age, MGA_BUFFER_USED, 0); 334 return next->buf; 335 } 336 337 DRM_DEBUG("returning NULL!\n"); 338 return NULL; 339} 340 341int mga_freelist_put(drm_device_t * dev, drm_buf_t * buf) 342{ 343 drm_mga_private_t *dev_priv = dev->dev_private; 344 drm_mga_buf_priv_t *buf_priv = buf->dev_private; 345 drm_mga_freelist_t *head, *entry, *prev; 346 347 DRM_DEBUG("age=0x%06lx wrap=%d\n", 348 buf_priv->list_entry->age.head - 349 dev_priv->primary->offset, buf_priv->list_entry->age.wrap); 350 351 entry = buf_priv->list_entry; 352 head = dev_priv->head; 353 354 if (buf_priv->list_entry->age.head == MGA_BUFFER_USED) { 355 SET_AGE(&entry->age, MGA_BUFFER_FREE, 0); 356 prev = dev_priv->tail; 357 prev->next = entry; 358 entry->prev = prev; 359 entry->next = NULL; 360 } else { 361 prev = head->next; 362 head->next = entry; 363 prev->prev = entry; 364 entry->prev = head; 365 entry->next = prev; 366 } 367 368 return 0; 369} 370 371/* ================================================================ 372 * DMA initialization, cleanup 373 */ 374 375int mga_driver_load(drm_device_t * dev, unsigned long flags) 376{ 377 drm_mga_private_t *dev_priv; 378 379 dev_priv = drm_alloc(sizeof(drm_mga_private_t), DRM_MEM_DRIVER); 380 if (!dev_priv) 381 return DRM_ERR(ENOMEM); 382 383 dev->dev_private = (void *)dev_priv; 384 memset(dev_priv, 0, sizeof(drm_mga_private_t)); 385 386 dev_priv->usec_timeout = MGA_DEFAULT_USEC_TIMEOUT; 387 dev_priv->chipset = flags; 388 389 dev_priv->mmio_base = drm_get_resource_start(dev, 1); 390 dev_priv->mmio_size = drm_get_resource_len(dev, 1); 391 392 dev->counters += 3; 393 dev->types[6] = _DRM_STAT_IRQ; 394 dev->types[7] = _DRM_STAT_PRIMARY; 395 dev->types[8] = _DRM_STAT_SECONDARY; 396 397 return 0; 398} 399 400#if __OS_HAS_AGP 401/** 402 * Bootstrap the driver for AGP DMA. 403 * 404 * \todo 405 * Investigate whether there is any benifit to storing the WARP microcode in 406 * AGP memory. If not, the microcode may as well always be put in PCI 407 * memory. 408 * 409 * \todo 410 * This routine needs to set dma_bs->agp_mode to the mode actually configured 411 * in the hardware. Looking just at the Linux AGP driver code, I don't see 412 * an easy way to determine this. 413 * 414 * \sa mga_do_dma_bootstrap, mga_do_pci_dma_bootstrap 415 */ 416static int mga_do_agp_dma_bootstrap(drm_device_t * dev, 417 drm_mga_dma_bootstrap_t * dma_bs) 418{ 419 drm_mga_private_t *const dev_priv = 420 (drm_mga_private_t *) dev->dev_private; 421 unsigned int warp_size = mga_warp_microcode_size(dev_priv); 422 int err; 423 unsigned offset; 424 const unsigned secondary_size = dma_bs->secondary_bin_count 425 * dma_bs->secondary_bin_size; 426 const unsigned agp_size = (dma_bs->agp_size << 20); 427 drm_buf_desc_t req; 428 drm_agp_mode_t mode; 429 drm_agp_info_t info; 430 drm_agp_buffer_t agp_req; 431 drm_agp_binding_t bind_req; 432 433 /* Acquire AGP. */ 434 err = drm_agp_acquire(dev); 435 if (err) { 436 DRM_ERROR("Unable to acquire AGP: %d\n", err); 437 return err; 438 } 439 440 err = drm_agp_info(dev, &info); 441 if (err) { 442 DRM_ERROR("Unable to get AGP info: %d\n", err); 443 return err; 444 } 445 446 mode.mode = (info.mode & ~0x07) | dma_bs->agp_mode; 447 err = drm_agp_enable(dev, mode); 448 if (err) { 449 DRM_ERROR("Unable to enable AGP (mode = 0x%lx)\n", mode.mode); 450 return err; 451 } 452 453 /* In addition to the usual AGP mode configuration, the G200 AGP cards 454 * need to have the AGP mode "manually" set. 455 */ 456 457 if (dev_priv->chipset == MGA_CARD_TYPE_G200) { 458 if (mode.mode & 0x02) { 459 MGA_WRITE(MGA_AGP_PLL, MGA_AGP2XPLL_ENABLE); 460 } else { 461 MGA_WRITE(MGA_AGP_PLL, MGA_AGP2XPLL_DISABLE); 462 } 463 } 464 465 /* Allocate and bind AGP memory. */ 466 agp_req.size = agp_size; 467 agp_req.type = 0; 468 err = drm_agp_alloc(dev, &agp_req); 469 if (err) { 470 dev_priv->agp_size = 0; 471 DRM_ERROR("Unable to allocate %uMB AGP memory\n", 472 dma_bs->agp_size); 473 return err; 474 } 475 476 dev_priv->agp_size = agp_size; 477 dev_priv->agp_handle = agp_req.handle; 478 479 bind_req.handle = agp_req.handle; 480 bind_req.offset = 0; 481 err = drm_agp_bind(dev, &bind_req); 482 if (err) { 483 DRM_ERROR("Unable to bind AGP memory: %d\n", err); 484 return err; 485 } 486 487 /* Make drm_addbufs happy by not trying to create a mapping for less 488 * than a page. 489 */ 490 if (warp_size < PAGE_SIZE) 491 warp_size = PAGE_SIZE; 492 493 offset = 0; 494 err = drm_addmap(dev, offset, warp_size, 495 _DRM_AGP, _DRM_READ_ONLY, &dev_priv->warp); 496 if (err) { 497 DRM_ERROR("Unable to map WARP microcode: %d\n", err); 498 return err; 499 } 500 501 offset += warp_size; 502 err = drm_addmap(dev, offset, dma_bs->primary_size, 503 _DRM_AGP, _DRM_READ_ONLY, &dev_priv->primary); 504 if (err) { 505 DRM_ERROR("Unable to map primary DMA region: %d\n", err); 506 return err; 507 } 508 509 offset += dma_bs->primary_size; 510 err = drm_addmap(dev, offset, secondary_size, 511 _DRM_AGP, 0, &dev->agp_buffer_map); 512 if (err) { 513 DRM_ERROR("Unable to map secondary DMA region: %d\n", err); 514 return err; 515 } 516 517 (void)memset(&req, 0, sizeof(req)); 518 req.count = dma_bs->secondary_bin_count; 519 req.size = dma_bs->secondary_bin_size; 520 req.flags = _DRM_AGP_BUFFER; 521 req.agp_start = offset; 522 523 err = drm_addbufs_agp(dev, &req); 524 if (err) { 525 DRM_ERROR("Unable to add secondary DMA buffers: %d\n", err); 526 return err; 527 } 528 529 { 530 drm_map_list_t *_entry; 531 unsigned long agp_token = 0; 532 533 list_for_each_entry(_entry, &dev->maplist->head, head) { 534 if (_entry->map == dev->agp_buffer_map) 535 agp_token = _entry->user_token; 536 } 537 if (!agp_token) 538 return -EFAULT; 539 540 dev->agp_buffer_token = agp_token; 541 } 542 543 offset += secondary_size; 544 err = drm_addmap(dev, offset, agp_size - offset, 545 _DRM_AGP, 0, &dev_priv->agp_textures); 546 if (err) { 547 DRM_ERROR("Unable to map AGP texture region %d\n", err); 548 return err; 549 } 550 551 drm_core_ioremap(dev_priv->warp, dev); 552 drm_core_ioremap(dev_priv->primary, dev); 553 drm_core_ioremap(dev->agp_buffer_map, dev); 554 555 if (!dev_priv->warp->handle || 556 !dev_priv->primary->handle || !dev->agp_buffer_map->handle) { 557 DRM_ERROR("failed to ioremap agp regions! (%p, %p, %p)\n", 558 dev_priv->warp->handle, dev_priv->primary->handle, 559 dev->agp_buffer_map->handle); 560 return DRM_ERR(ENOMEM); 561 } 562 563 dev_priv->dma_access = MGA_PAGPXFER; 564 dev_priv->wagp_enable = MGA_WAGP_ENABLE; 565 566 DRM_INFO("Initialized card for AGP DMA.\n"); 567 return 0; 568} 569#else 570static int mga_do_agp_dma_bootstrap(drm_device_t * dev, 571 drm_mga_dma_bootstrap_t * dma_bs) 572{ 573 return -EINVAL; 574} 575#endif 576 577/** 578 * Bootstrap the driver for PCI DMA. 579 * 580 * \todo 581 * The algorithm for decreasing the size of the primary DMA buffer could be 582 * better. The size should be rounded up to the nearest page size, then 583 * decrease the request size by a single page each pass through the loop. 584 * 585 * \todo 586 * Determine whether the maximum address passed to drm_pci_alloc is correct. 587 * The same goes for drm_addbufs_pci. 588 * 589 * \sa mga_do_dma_bootstrap, mga_do_agp_dma_bootstrap 590 */ 591static int mga_do_pci_dma_bootstrap(drm_device_t * dev, 592 drm_mga_dma_bootstrap_t * dma_bs) 593{ 594 drm_mga_private_t *const dev_priv = 595 (drm_mga_private_t *) dev->dev_private; 596 unsigned int warp_size = mga_warp_microcode_size(dev_priv); 597 unsigned int primary_size; 598 unsigned int bin_count; 599 int err; 600 drm_buf_desc_t req; 601 602 if (dev->dma == NULL) { 603 DRM_ERROR("dev->dma is NULL\n"); 604 return DRM_ERR(EFAULT); 605 } 606 607 /* Make drm_addbufs happy by not trying to create a mapping for less 608 * than a page. 609 */ 610 if (warp_size < PAGE_SIZE) 611 warp_size = PAGE_SIZE; 612 613 /* The proper alignment is 0x100 for this mapping */ 614 err = drm_addmap(dev, 0, warp_size, _DRM_CONSISTENT, 615 _DRM_READ_ONLY, &dev_priv->warp); 616 if (err != 0) { 617 DRM_ERROR("Unable to create mapping for WARP microcode: %d\n", 618 err); 619 return err; 620 } 621 622 /* Other than the bottom two bits being used to encode other 623 * information, there don't appear to be any restrictions on the 624 * alignment of the primary or secondary DMA buffers. 625 */ 626 627 for (primary_size = dma_bs->primary_size; primary_size != 0; 628 primary_size >>= 1) { 629 /* The proper alignment for this mapping is 0x04 */ 630 err = drm_addmap(dev, 0, primary_size, _DRM_CONSISTENT, 631 _DRM_READ_ONLY, &dev_priv->primary); 632 if (!err) 633 break; 634 } 635 636 if (err != 0) { 637 DRM_ERROR("Unable to allocate primary DMA region: %d\n", err); 638 return DRM_ERR(ENOMEM); 639 } 640 641 if (dev_priv->primary->size != dma_bs->primary_size) { 642 DRM_INFO("Primary DMA buffer size reduced from %u to %u.\n", 643 dma_bs->primary_size, 644 (unsigned)dev_priv->primary->size); 645 dma_bs->primary_size = dev_priv->primary->size; 646 } 647 648 for (bin_count = dma_bs->secondary_bin_count; bin_count > 0; 649 bin_count--) { 650 (void)memset(&req, 0, sizeof(req)); 651 req.count = bin_count; 652 req.size = dma_bs->secondary_bin_size; 653 654 err = drm_addbufs_pci(dev, &req); 655 if (!err) { 656 break; 657 } 658 } 659 660 if (bin_count == 0) { 661 DRM_ERROR("Unable to add secondary DMA buffers: %d\n", err); 662 return err; 663 } 664 665 if (bin_count != dma_bs->secondary_bin_count) { 666 DRM_INFO("Secondary PCI DMA buffer bin count reduced from %u " 667 "to %u.\n", dma_bs->secondary_bin_count, bin_count); 668 669 dma_bs->secondary_bin_count = bin_count; 670 } 671 672 dev_priv->dma_access = 0; 673 dev_priv->wagp_enable = 0; 674 675 dma_bs->agp_mode = 0; 676 677 DRM_INFO("Initialized card for PCI DMA.\n"); 678 return 0; 679} 680 681static int mga_do_dma_bootstrap(drm_device_t * dev, 682 drm_mga_dma_bootstrap_t * dma_bs) 683{ 684 const int is_agp = (dma_bs->agp_mode != 0) && drm_device_is_agp(dev); 685 int err; 686 drm_mga_private_t *const dev_priv = 687 (drm_mga_private_t *) dev->dev_private; 688 689 dev_priv->used_new_dma_init = 1; 690 691 /* The first steps are the same for both PCI and AGP based DMA. Map 692 * the cards MMIO registers and map a status page. 693 */ 694 err = drm_addmap(dev, dev_priv->mmio_base, dev_priv->mmio_size, 695 _DRM_REGISTERS, _DRM_READ_ONLY, &dev_priv->mmio); 696 if (err) { 697 DRM_ERROR("Unable to map MMIO region: %d\n", err); 698 return err; 699 } 700 701 err = drm_addmap(dev, 0, SAREA_MAX, _DRM_SHM, 702 _DRM_READ_ONLY | _DRM_LOCKED | _DRM_KERNEL, 703 &dev_priv->status); 704 if (err) { 705 DRM_ERROR("Unable to map status region: %d\n", err); 706 return err; 707 } 708 709 /* The DMA initialization procedure is slightly different for PCI and 710 * AGP cards. AGP cards just allocate a large block of AGP memory and 711 * carve off portions of it for internal uses. The remaining memory 712 * is returned to user-mode to be used for AGP textures. 713 */ 714 if (is_agp) { 715 err = mga_do_agp_dma_bootstrap(dev, dma_bs); 716 } 717 718 /* If we attempted to initialize the card for AGP DMA but failed, 719 * clean-up any mess that may have been created. 720 */ 721 722 if (err) { 723 mga_do_cleanup_dma(dev, MINIMAL_CLEANUP); 724 } 725 726 /* Not only do we want to try and initialized PCI cards for PCI DMA, 727 * but we also try to initialized AGP cards that could not be 728 * initialized for AGP DMA. This covers the case where we have an AGP 729 * card in a system with an unsupported AGP chipset. In that case the 730 * card will be detected as AGP, but we won't be able to allocate any 731 * AGP memory, etc. 732 */ 733 734 if (!is_agp || err) { 735 err = mga_do_pci_dma_bootstrap(dev, dma_bs); 736 } 737 738 return err; 739} 740 741int mga_dma_bootstrap(DRM_IOCTL_ARGS) 742{ 743 DRM_DEVICE; 744 drm_mga_dma_bootstrap_t bootstrap; 745 int err; 746 static const int modes[] = { 0, 1, 2, 2, 4, 4, 4, 4 }; 747 const drm_mga_private_t *const dev_priv = 748 (drm_mga_private_t *) dev->dev_private; 749 750 DRM_COPY_FROM_USER_IOCTL(bootstrap, 751 (drm_mga_dma_bootstrap_t __user *) data, 752 sizeof(bootstrap)); 753 754 err = mga_do_dma_bootstrap(dev, &bootstrap); 755 if (err) { 756 mga_do_cleanup_dma(dev, FULL_CLEANUP); 757 return err; 758 } 759 760 if (dev_priv->agp_textures != NULL) { 761 bootstrap.texture_handle = dev_priv->agp_textures->offset; 762 bootstrap.texture_size = dev_priv->agp_textures->size; 763 } else { 764 bootstrap.texture_handle = 0; 765 bootstrap.texture_size = 0; 766 } 767 768 bootstrap.agp_mode = modes[bootstrap.agp_mode & 0x07]; 769 DRM_COPY_TO_USER_IOCTL((drm_mga_dma_bootstrap_t __user *)data, 770 bootstrap, sizeof(bootstrap)); 771 772 return err; 773} 774 775static int mga_do_init_dma(drm_device_t * dev, drm_mga_init_t * init) 776{ 777 drm_mga_private_t *dev_priv; 778 int ret; 779 DRM_DEBUG("\n"); 780 781 dev_priv = dev->dev_private; 782 783 if (init->sgram) { 784 dev_priv->clear_cmd = MGA_DWGCTL_CLEAR | MGA_ATYPE_BLK; 785 } else { 786 dev_priv->clear_cmd = MGA_DWGCTL_CLEAR | MGA_ATYPE_RSTR; 787 } 788 dev_priv->maccess = init->maccess; 789 790 dev_priv->fb_cpp = init->fb_cpp; 791 dev_priv->front_offset = init->front_offset; 792 dev_priv->front_pitch = init->front_pitch; 793 dev_priv->back_offset = init->back_offset; 794 dev_priv->back_pitch = init->back_pitch; 795 796 dev_priv->depth_cpp = init->depth_cpp; 797 dev_priv->depth_offset = init->depth_offset; 798 dev_priv->depth_pitch = init->depth_pitch; 799 800 dev_priv->texture_offset = init->texture_offset[0]; 801 dev_priv->texture_size = init->texture_size[0]; 802 803 DRM_GETSAREA(); 804 805 if (!dev_priv->sarea) { 806 DRM_ERROR("failed to find sarea!\n"); 807 return DRM_ERR(EINVAL); 808 } 809 810 if (!dev_priv->used_new_dma_init) { 811 812 dev_priv->dma_access = MGA_PAGPXFER; 813 dev_priv->wagp_enable = MGA_WAGP_ENABLE; 814 815 dev_priv->status = drm_core_findmap(dev, init->status_offset); 816 if (!dev_priv->status) { 817 DRM_ERROR("failed to find status page!\n"); 818 return DRM_ERR(EINVAL); 819 } 820 dev_priv->mmio = drm_core_findmap(dev, init->mmio_offset); 821 if (!dev_priv->mmio) { 822 DRM_ERROR("failed to find mmio region!\n"); 823 return DRM_ERR(EINVAL); 824 } 825 dev_priv->warp = drm_core_findmap(dev, init->warp_offset); 826 if (!dev_priv->warp) { 827 DRM_ERROR("failed to find warp microcode region!\n"); 828 return DRM_ERR(EINVAL); 829 } 830 dev_priv->primary = drm_core_findmap(dev, init->primary_offset); 831 if (!dev_priv->primary) { 832 DRM_ERROR("failed to find primary dma region!\n"); 833 return DRM_ERR(EINVAL); 834 } 835 dev->agp_buffer_token = init->buffers_offset; 836 dev->agp_buffer_map = 837 drm_core_findmap(dev, init->buffers_offset); 838 if (!dev->agp_buffer_map) { 839 DRM_ERROR("failed to find dma buffer region!\n"); 840 return DRM_ERR(EINVAL); 841 } 842 843 drm_core_ioremap(dev_priv->warp, dev); 844 drm_core_ioremap(dev_priv->primary, dev); 845 drm_core_ioremap(dev->agp_buffer_map, dev); 846 } 847 848 dev_priv->sarea_priv = 849 (drm_mga_sarea_t *) ((u8 *) dev_priv->sarea->handle + 850 init->sarea_priv_offset); 851 852 if (!dev_priv->warp->handle || 853 !dev_priv->primary->handle || 854 ((dev_priv->dma_access != 0) && 855 ((dev->agp_buffer_map == NULL) || 856 (dev->agp_buffer_map->handle == NULL)))) { 857 DRM_ERROR("failed to ioremap agp regions!\n"); 858 return DRM_ERR(ENOMEM); 859 } 860 861 ret = mga_warp_install_microcode(dev_priv); 862 if (ret < 0) { 863 DRM_ERROR("failed to install WARP ucode!: %d\n", ret); 864 return ret; 865 } 866 867 ret = mga_warp_init(dev_priv); 868 if (ret < 0) { 869 DRM_ERROR("failed to init WARP engine!: %d\n", ret); 870 return ret; 871 } 872 873 dev_priv->prim.status = (u32 *) dev_priv->status->handle; 874 875 mga_do_wait_for_idle(dev_priv); 876 877 /* Init the primary DMA registers. 878 */ 879 MGA_WRITE(MGA_PRIMADDRESS, dev_priv->primary->offset | MGA_DMA_GENERAL); 880 881 dev_priv->prim.start = (u8 *) dev_priv->primary->handle; 882 dev_priv->prim.end = ((u8 *) dev_priv->primary->handle 883 + dev_priv->primary->size); 884 dev_priv->prim.size = dev_priv->primary->size; 885 886 dev_priv->prim.tail = 0; 887 dev_priv->prim.space = dev_priv->prim.size; 888 dev_priv->prim.wrapped = 0; 889 890 dev_priv->prim.last_flush = 0; 891 dev_priv->prim.last_wrap = 0; 892 893 dev_priv->prim.high_mark = 256 * DMA_BLOCK_SIZE; 894 895 dev_priv->prim.status[0] = dev_priv->primary->offset; 896 dev_priv->prim.status[1] = 0; 897 898 dev_priv->sarea_priv->last_wrap = 0; 899 dev_priv->sarea_priv->last_frame.head = 0; 900 dev_priv->sarea_priv->last_frame.wrap = 0; 901 902 if (mga_freelist_init(dev, dev_priv) < 0) { 903 DRM_ERROR("could not initialize freelist\n"); 904 return DRM_ERR(ENOMEM); 905 } 906 907 return 0; 908} 909 910static int mga_do_cleanup_dma(drm_device_t *dev, int full_cleanup) 911{ 912 int err = 0; 913 DRM_DEBUG("\n"); 914 915 /* Make sure interrupts are disabled here because the uninstall ioctl 916 * may not have been called from userspace and after dev_private 917 * is freed, it's too late. 918 */ 919 if (dev->irq_enabled) 920 drm_irq_uninstall(dev); 921 922 if (dev->dev_private) { 923 drm_mga_private_t *dev_priv = dev->dev_private; 924 925 if ((dev_priv->warp != NULL) 926 && (dev_priv->warp->type != _DRM_CONSISTENT)) 927 drm_core_ioremapfree(dev_priv->warp, dev); 928 929 if ((dev_priv->primary != NULL) 930 && (dev_priv->primary->type != _DRM_CONSISTENT)) 931 drm_core_ioremapfree(dev_priv->primary, dev); 932 933 if (dev->agp_buffer_map != NULL) 934 drm_core_ioremapfree(dev->agp_buffer_map, dev); 935 936 if (dev_priv->used_new_dma_init) { 937#if __OS_HAS_AGP 938 if (dev_priv->agp_handle != 0) { 939 drm_agp_binding_t unbind_req; 940 drm_agp_buffer_t free_req; 941 942 unbind_req.handle = dev_priv->agp_handle; 943 drm_agp_unbind(dev, &unbind_req); 944 945 free_req.handle = dev_priv->agp_handle; 946 drm_agp_free(dev, &free_req); 947 948 dev_priv->agp_textures = NULL; 949 dev_priv->agp_size = 0; 950 dev_priv->agp_handle = 0; 951 } 952 953 if ((dev->agp != NULL) && dev->agp->acquired) { 954 err = drm_agp_release(dev); 955 } 956#endif 957 } 958 959 dev_priv->warp = NULL; 960 dev_priv->primary = NULL; 961 dev_priv->sarea = NULL; 962 dev_priv->sarea_priv = NULL; 963 dev->agp_buffer_map = NULL; 964 965 if (full_cleanup) { 966 dev_priv->mmio = NULL; 967 dev_priv->status = NULL; 968 dev_priv->used_new_dma_init = 0; 969 } 970 971 memset(&dev_priv->prim, 0, sizeof(dev_priv->prim)); 972 dev_priv->warp_pipe = 0; 973 memset(dev_priv->warp_pipe_phys, 0, 974 sizeof(dev_priv->warp_pipe_phys)); 975 976 if (dev_priv->head != NULL) { 977 mga_freelist_cleanup(dev); 978 } 979 } 980 981 return 0; 982} 983 984int mga_dma_init(DRM_IOCTL_ARGS) 985{ 986 DRM_DEVICE; 987 drm_mga_init_t init; 988 int err; 989 990 LOCK_TEST_WITH_RETURN(dev, filp); 991 992 DRM_COPY_FROM_USER_IOCTL(init, (drm_mga_init_t __user *) data, 993 sizeof(init)); 994 995 switch (init.func) { 996 case MGA_INIT_DMA: 997 err = mga_do_init_dma(dev, &init); 998 if (err) { 999 (void)mga_do_cleanup_dma(dev, FULL_CLEANUP); 1000 } 1001 return err; 1002 case MGA_CLEANUP_DMA: 1003 return mga_do_cleanup_dma(dev, FULL_CLEANUP); 1004 } 1005 1006 return DRM_ERR(EINVAL); 1007} 1008 1009/* ================================================================ 1010 * Primary DMA stream management 1011 */ 1012 1013int mga_dma_flush(DRM_IOCTL_ARGS) 1014{ 1015 DRM_DEVICE; 1016 drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private; 1017 drm_lock_t lock; 1018 1019 LOCK_TEST_WITH_RETURN(dev, filp); 1020 1021 DRM_COPY_FROM_USER_IOCTL(lock, (drm_lock_t __user *) data, 1022 sizeof(lock)); 1023 1024 DRM_DEBUG("%s%s%s\n", 1025 (lock.flags & _DRM_LOCK_FLUSH) ? "flush, " : "", 1026 (lock.flags & _DRM_LOCK_FLUSH_ALL) ? "flush all, " : "", 1027 (lock.flags & _DRM_LOCK_QUIESCENT) ? "idle, " : ""); 1028 1029 WRAP_WAIT_WITH_RETURN(dev_priv); 1030 1031 if (lock.flags & (_DRM_LOCK_FLUSH | _DRM_LOCK_FLUSH_ALL)) { 1032 mga_do_dma_flush(dev_priv); 1033 } 1034 1035 if (lock.flags & _DRM_LOCK_QUIESCENT) { 1036#if MGA_DMA_DEBUG 1037 int ret = mga_do_wait_for_idle(dev_priv); 1038 if (ret < 0) 1039 DRM_INFO("%s: -EBUSY\n", __FUNCTION__); 1040 return ret; 1041#else 1042 return mga_do_wait_for_idle(dev_priv); 1043#endif 1044 } else { 1045 return 0; 1046 } 1047} 1048 1049int mga_dma_reset(DRM_IOCTL_ARGS) 1050{ 1051 DRM_DEVICE; 1052 drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private; 1053 1054 LOCK_TEST_WITH_RETURN(dev, filp); 1055 1056 return mga_do_dma_reset(dev_priv); 1057} 1058 1059/* ================================================================ 1060 * DMA buffer management 1061 */ 1062 1063static int mga_dma_get_buffers(DRMFILE filp, drm_device_t * dev, drm_dma_t * d) 1064{ 1065 drm_buf_t *buf; 1066 int i; 1067 1068 for (i = d->granted_count; i < d->request_count; i++) { 1069 buf = mga_freelist_get(dev); 1070 if (!buf) 1071 return DRM_ERR(EAGAIN); 1072 1073 buf->filp = filp; 1074 1075 if (DRM_COPY_TO_USER(&d->request_indices[i], 1076 &buf->idx, sizeof(buf->idx))) 1077 return DRM_ERR(EFAULT); 1078 if (DRM_COPY_TO_USER(&d->request_sizes[i], 1079 &buf->total, sizeof(buf->total))) 1080 return DRM_ERR(EFAULT); 1081 1082 d->granted_count++; 1083 } 1084 return 0; 1085} 1086 1087int mga_dma_buffers(DRM_IOCTL_ARGS) 1088{ 1089 DRM_DEVICE; 1090 drm_device_dma_t *dma = dev->dma; 1091 drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private; 1092 drm_dma_t __user *argp = (void __user *)data; 1093 drm_dma_t d; 1094 int ret = 0; 1095 1096 LOCK_TEST_WITH_RETURN(dev, filp); 1097 1098 DRM_COPY_FROM_USER_IOCTL(d, argp, sizeof(d)); 1099 1100 /* Please don't send us buffers. 1101 */ 1102 if (d.send_count != 0) { 1103 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n", 1104 DRM_CURRENTPID, d.send_count); 1105 return DRM_ERR(EINVAL); 1106 } 1107 1108 /* We'll send you buffers. 1109 */ 1110 if (d.request_count < 0 || d.request_count > dma->buf_count) { 1111 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n", 1112 DRM_CURRENTPID, d.request_count, dma->buf_count); 1113 return DRM_ERR(EINVAL); 1114 } 1115 1116 WRAP_TEST_WITH_RETURN(dev_priv); 1117 1118 d.granted_count = 0; 1119 1120 if (d.request_count) { 1121 ret = mga_dma_get_buffers(filp, dev, &d); 1122 } 1123 1124 DRM_COPY_TO_USER_IOCTL(argp, d, sizeof(d)); 1125 1126 return ret; 1127} 1128 1129/** 1130 * Called just before the module is unloaded. 1131 */ 1132int mga_driver_unload(drm_device_t * dev) 1133{ 1134 drm_free(dev->dev_private, sizeof(drm_mga_private_t), DRM_MEM_DRIVER); 1135 dev->dev_private = NULL; 1136 1137 return 0; 1138} 1139 1140/** 1141 * Called when the last opener of the device is closed. 1142 */ 1143void mga_driver_lastclose(drm_device_t * dev) 1144{ 1145 mga_do_cleanup_dma(dev, FULL_CLEANUP); 1146} 1147 1148int mga_driver_dma_quiescent(drm_device_t * dev) 1149{ 1150 drm_mga_private_t *dev_priv = dev->dev_private; 1151 return mga_do_wait_for_idle(dev_priv); 1152} 1153